Re: Slow FIFO using external SRAM

I would design a reasonably fast state machine ( 50 MHz?) that keeps
track of the read and write requests, updates the two addresses and
multiplexes them appropriately to the external SRAM. If read-access
time is important, you could always pre-fetch the next entry and store
it in an on-chip register. The state machine must check for the two
addresses becoming equal. If read causes them to become equal, the FIFO
is empty, if write causes it, the FIFO is full.
The slow speed makes all this possible, and even easy.
Don't worry too much about metastability of the control circuitry. Just
make sure that there is an extra 5 ns of settling-time slack available.
Peter Alfke, Xilinx Applications

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Relevant Pages

  • Re: OPB or FSL?
    ... The read and write FIFO is synschrounous to your microblaze clock. ... I think it is a single cycle instruction to to a non-blocking write to a FSL. ... The rest of the speed is dependent our your state machine to grab data about of the FIFO and move it elsewhere. ... If you wish to do OPB master transactions from a peripheral on the bus, I would recommend just reading the OPB spec and making your own piece of IP. ...
    (comp.arch.fpga)
  • Re: Linux 2.6.25-rc4
    ... The state machine on the ... promise for example empties the FIFO and if you touch the data port again ...
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  • Re: Slow FIFO using external SRAM
    ... > track of the read and write requests, updates the two addresses and ... The state machine must check for the two ... If read causes them to become equal, the FIFO ...
    (comp.arch.fpga)