Re: async fifo design

Hi,

I would synchonise the gray output of each domain first using two register stages in series and apply the gray to binary conversion AFTER the synchronisation. This will give you a glitch safety good enough for any industial environment. If the synchronisation does glitch, then only in the single bit which the receiving clock domain might perceive as changing. (If you synchronise the converted value, the receiving clock domain could observe multiple simultaneous changes)

Something like the VHDL pseudo-code below:


signal count_clka..
signal count_clkb..
signal counta_sync1_clkb, counta_sync2_clkb..
signal countb_sync1_clka, countb_sync2_clka..

    -- synchronising clka to the clkb domain
process (clkb, rst_n)
  variable v_counta_sync_binary...
  variable v_countb_clkb_binary...
begin
  if (clkb'event and (clkb = '1')) then
        -- convert the local counter
    v_countb_clkb_binary := f_gray_to_bin(count_clkb);
        -- convert the synchronised remote counter
    v_counta_sync_binary := f_gray_to_bin(counta_sync2_clkb);

      -- do the comparison stuff between v_countb_clkb_binary and
      -- v_counta_sync_binary
      -- e.g. setting up the new values for full/empty etc.
 		. . . .

      -- update the synchronising stages		
    counta_sync1_clkb <= count_clka;
    counta_sync2_clkb <= counta_sync1_clkb;
	. . . .
end process;

-- and of course a similar process for the other direction
.