Re: Virtex 4 Tapped Delay Lines
- From: Philip Freidin <philip@xxxxxxxxxxxxxxx>
- Date: Mon, 28 Nov 2005 15:00:08 GMT
On Mon, 28 Nov 2005 03:15:36 -0600, alastairlynch@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx (al99999) wrote:
>Thanks for all your help. One quick last question, is it possible to
>internally connect the pins, or do I need to physically wire them up
>external to the fpga? Thanks again,
>
>Alastair
You could bring the signal in on 1 pin, and then setup 8 other
I/Os as bi directional, and send the signal out on all 8, and
then bring it back in on those 8, with the IDELAY stuff. Doing
this will make the external pins wiggle, so they would all have
to be "no connection" externally.
Overall, I would not recommend this structure, as you will not
have good control of the delay to each of the output circuits,
and this would therefore add to the error in timing.
I think it is best to distribute the signal on your PCB.
Philip
.
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