Re: async fifo design
- From: "Charles, NG" <site_blackhole@xxxxxxxxxxxx>
- Date: Mon, 28 Nov 2005 11:08:21 +0100
Hi,
1) A gray-to-binary code that I picked up on the web years ago is
------------------------------------------------------------
function f_gray_to_bin(vval : std_logic_vector) return std_logic_vector is
variable i : integer;
variable v_accumulate : std_logic_vector(vval'left downto vval'right);
variable v_par1 : std_logic_vector(vval'length - 1 downto 0);
begin
v_par1 := vval;
v_accumulate(v_par1'left) := v_par1(v_par1'left);
for i in v_par1'left -1 downto 0 loop
v_accumulate(i) := v_par1(i) xor v_accumulate(i + 1);
end loop;
return v_accumulate;
end f_gray_to_bin;
------------------------------------------------------------
I can't find the document I derived it from on my laptop, I still should have it on a CD somewhere. If I get a chance to look I'll send it to you.
2) Seems a difficult one at first glance.
Would it be feasable
a) just to store the base addresses on the FIFO (since the packet or whatever always seems to be 18 bytes)
b) use semaphores to indicate whether memory blocks are empty/valid/read .
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