Re: Anybody understand this ISE 7.1 error, and what to do about it???
- From: Ray Andraka <ray@xxxxxxxxxxx>
- Date: Sun, 06 Nov 2005 21:01:45 -0500
GaLaKtIkUs™ wrote:
Its because of the users Xilinx polled, most either didn't use SRL16's at all or if they did used less than 5% of the LUTs as SRL16s/RAM. The SRL16 is not free, it substantially increases the physical area occupied by the LUT, as well as the testing required to verify the part 100%, so Xilinx took the opportunity to reduce the complexity by stripping out half the distributed memory elements. I think a large part of the fault lies in the fact that Xilinx does a very poor job of touting the benefits of the SRL16 capability, in fact, I don't think they have more than a few people there that understand how powerful this element is. It is a shame they stripped it out of half the part, and I think it makes the software that much harder as well. They don't really feel the pain though because their top shelf users are not really using the capability effectively, and synthesis only makes use of it in the most rudimentary way.But why were these changes done ? is it a sacrifice made by Xilinx to allow adding XtremeDSP and other hard cores inside the Virtex-4 ? Or is it simply because a few people use the CLBs as memory or shift registers?
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--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@xxxxxxxxxxx http://www.andraka.com
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