comp.arch.fpga

Date Index

Clock problem? Altera Stratix-II ES and MP, Tomoya
Xilinx Coregen IP Customizer Causes Exception During Customization, juendme
Q-bus or Unibus bus transactions in FPGA?, Richard
- Re: Q-bus or Unibus bus transactions in FPGA?, Jon Elson
  - Re: Q-bus or Unibus bus transactions in FPGA?, Richard
    - Re: Q-bus or Unibus bus transactions in FPGA?, Hal Murray
    - Re: Q-bus or Unibus bus transactions in FPGA?, GPE
- Re: Q-bus or Unibus bus transactions in FPGA?, GPE
Bit-serial arithmetic on Spartan II, Richard
nallatech benone fpga board, g.wall
- Re: nallatech benone fpga board, PeteS
Successful use of MGT on Virtex 4, JarJarJP12
grabbing PCI signals, rev-eng dev board, g.wall
- Re: grabbing PCI signals, rev-eng dev board, Kareltje
- Re: grabbing PCI signals, rev-eng dev board, Krzysztof Przednowek
first time managing a project, gretzteam
- Re: first time managing a project, John Adair
- Re: first time managing a project, amyler
  - Re: first time managing a project, Tim Wescott
- Re: first time managing a project, Tim Wescott
  - Re: first time managing a project, Hal Murray
    - Re: first time managing a project, amyler
    - Re: first time managing a project, PeteS
- Re: first time managing a project, Bob Perlman
ISE question on whats a "X_LUT3"?, Fred
- Re: ISE question on whats a "X_LUT3"?, Duane Clark
  - Re: ISE question on whats a "X_LUT3"?, Fred
The reason of implementation of morphological operator in FPGA, TMU
- Re: The reason of implementation of morphological operator in FPGA, Brad Smallridge
Slow FIFO using external SRAM, damir
- Re: Slow FIFO using external SRAM, Andy Peters
  - Re: Slow FIFO using external SRAM, Peter Alfke
    - Re: Slow FIFO using external SRAM, damir
  - Re: Slow FIFO using external SRAM, Jim Granville
  - Re: Slow FIFO using external SRAM, Ray Andraka
    - Re: Slow FIFO using external SRAM, Andy Peters
- Re: Slow FIFO using external SRAM, Arlet
Merging the ML403 refence design and the GSRD design, electronics_designer
- re:Merging the ML403 refence design and the GSRD design, leevv
DCM Wizard, rsriragh
- re:DCM Wizard, seb_tech_fr
- <Possible follow-ups>
- DCM Wizard, rsriragh
Xilinx 'unconstrained period' problem, johnp
- Re: Xilinx 'unconstrained period' problem, Gabor
  - Re: Xilinx 'unconstrained period' problem, johnp
ML403 GPIO Switch not present, GaLaKtIkUs?
- Re: ML403 GPIO Switch not present, GaLaKtIkUs?
HDL Chip Design, Tori
- Re: HDL Chip Design, Symon
instruction counts and cache hits/misses on FPGA, Pankaj
- Re: instruction counts and cache hits/misses on FPGA, Martin Schoeberl
  - Re: instruction counts and cache hits/misses on FPGA, Joseph Samson
    - Re: instruction counts and cache hits/misses on FPGA, Paul Hartke
    - Re: instruction counts and cache hits/misses on FPGA, Kunal Shenoy
  - Re: instruction counts and cache hits/misses on FPGA, Kolja Sulimma
Altera Pin not used in Quartus project but drives logic, Monica
- Re: Altera Pin not used in Quartus project but drives logic, Mike Treseler
- Re: Altera Pin not used in Quartus project but drives logic, henn_xxx@xxxxxxxxxxx
boot from flah, Athena
- Re: boot from flah, PeteS
- Re: boot from flah, Athena
  - Re: boot from flah, Carsten
    - Re: boot from flah, PeteS
- Re: boot from flah, Athena
async fifo design, Michael Dreschmann
- Re: async fifo design, Charles, NG
  - Re: async fifo design, Michael Dreschmann
    - Re: async fifo design, C. G.
    - Re: async fifo design, Peter Alfke
    - Re: async fifo design, Michael Dreschmann
    - Re: async fifo design, Peter Alfke
    - Re: async fifo design, Hal Murray
Virtex 4 Configuration, Enzo Guerra
- Re: Virtex 4 Configuration, Bob
  - Re: Virtex 4 Configuration, Hal Murray
    - Re: Virtex 4 Configuration, Bob
VLSI Processor Cores, ABS
- Re: VLSI Processor Cores, John Adair
Virtex 4 Tapped Delay Lines, al99999
- Re: Virtex 4 Tapped Delay Lines, Philip Freidin
  - Re: Virtex 4 Tapped Delay Lines, al99999
- Re: Virtex 4 Tapped Delay Lines, al99999
  - Re: Virtex 4 Tapped Delay Lines, Peter Alfke
    - Re: Virtex 4 Tapped Delay Lines, Jim Granville
    - Re: Virtex 4 Tapped Delay Lines, Peter Alfke
  - Re: Virtex 4 Tapped Delay Lines, Philip Freidin
- re:Virtex 4 Tapped Delay Lines, al99999
  - Re: Virtex 4 Tapped Delay Lines, Philip Freidin
    - Re: Virtex 4 Tapped Delay Lines, Symon
    - Re: Virtex 4 Tapped Delay Lines, Symon
    - Re: Virtex 4 Tapped Delay Lines, Peter Alfke
Xilinx timing constraint question, johnp
- <Possible follow-ups>
- Xilinx timing constraint question, johnp
- Xilinx timing constraint question, johnp
- Xilinx timing constraint question, johnp
- Xilinx timing constraint question, johnp
Distributed RAMs / SRL: Why not, Altera?, Michael Kramer
- Re: Distributed RAMs / SRL: Why not, Altera?, John Adair
  - Re: Distributed RAMs / SRL: Why not, Altera?, Simon Peacock
  - Re: Distributed RAMs / SRL: Why not, Altera?, Michael Kramer
    - Re: Distributed RAMs / SRL: Why not, Altera?, Mike Harrison
    - Re: Distributed RAMs / SRL: Why not, Altera?, John Adair
    - Re: Distributed RAMs / SRL: Why not, Altera?, Mike Treseler
    - Re: Distributed RAMs / SRL: Why not, Altera?, Michael Kramer
    - Re: Distributed RAMs / SRL: Why not, Altera?, Mike Treseler
RocketChips?, altera_smells
virtex 4 extreme DSP linux PCI driver, g.wall
LF: XC4VFX20 samples, MM
- Re: XC4VFX20 samples, Antti Lukats
  - Re: XC4VFX20 samples, altera_smells
access to phase accumulator in Xilinx DDS 5.0, Gerhard Hoffmann
subtractor, Olaf Petzold
- Re: subtractor, Olaf Petzold
- Re: subtractor, Olaf Petzold
  - Re: subtractor, backhus
- Re: subtractor, Olaf Petzold
- Re: subtractor, backhus
- Re: subtractor, Olaf Petzold
  - Re: subtractor, Andy Peters
  - Re: subtractor, backhus
Convert Enumeration to Integer, Olaf Petzold
Mobile Chips, rohit . tripathy
- Re: Mobile Chips, PeteS
PLB GEMAC, solazzimarco
How to tell which synthesis tool I am using, mark andrew
EDK from ISE, Raymond
Partial Reconfiguration Problems, David Kramer
Configuration PROM XC18V02 bit error, Lars
- Re: Configuration PROM XC18V02 bit error, PeteS
  - Re: Configuration PROM XC18V02 bit error, Lars
Black Box Attribute in Quartus II, kedarpapte
MapLib error for EDK application, milind
Speed of programming for xc18v04?, Frank, Frank
- Re: Speed of programming for xc18v04?, Frank, Frank
- Re: Speed of programming for xc18v04?, John Adair
ChipScope 7.1 w/ EDK 7.1 data port bit ordering issue, Nju Njoroge
- Re: ChipScope 7.1 w/ EDK 7.1 data port bit ordering issue, John_H
XST :division and mod in vhdl, Okashii
- Re: XST :division and mod in vhdl, Stephane
  - Re: XST :division and mod in vhdl, Okashii
    - Re: XST :division and mod in vhdl, allanherriman
    - Re: XST :division and mod in vhdl, Okashii
    - Re: XST :division and mod in vhdl, Stephane
    - Re: XST :division and mod in vhdl, Philip Freidin
    - Re: XST :division and mod in vhdl, Simon Peacock
FPGA ARM IP Core, Antti Lukats
- Re: FPGA ARM IP Core, langwadt
- Re: FPGA ARM IP Core, Jim Granville
- Re: FPGA ARM IP Core, Thomas Entner
accessing the phase accumulator in Xilinx DDS 5.0, Gerhard Hoffmann
simulating code loading in memory and jumping to memory, sjulhes
- Re: simulating code loading in memory and jumping to memory, googlie
  - Re: simulating code loading in memory and jumping to memory, sjulhes
    - Re: simulating code loading in memory and jumping to memory, googlie
    - Re: simulating code loading in memory and jumping to memory, beeraka@xxxxxxxxx
    - Re: simulating code loading in memory and jumping to memory, sjulhes
    - Re: simulating code loading in memory and jumping to memory, beeraka@xxxxxxxxx
    - Re: simulating code loading in memory and jumping to memory, sjulhes
Memory in VHDL, Martin Schoeberl
- Re: Memory in VHDL, Martin Schoeberl
  - Re: Memory in VHDL, John Adair
    - Re: Memory in VHDL, Martin Schoeberl
    - Re: Memory in VHDL, John Adair
  - Re: Memory in VHDL, Aurelian Lazarut
    - Re: Memory in VHDL, Martin Schoeberl
    - Re: Memory in VHDL, Martin Thompson
    - Re: Memory in VHDL, Martin Schoeberl
  - Re: Memory in VHDL, Olaf Petzold
    - Re: Memory in VHDL, Martin Schoeberl
  - Re: Memory in VHDL, Martin Thompson
  - Re: Memory in VHDL, Ray Andraka
    - Re: Memory in VHDL, fjh-mailbox-38@xxxxxxxxxx
- re:Memory in VHDL, ralfsmith
case statement fault, Marco
- Re: case statement fault, Tim Good
  - Re: case statement fault, Marco
Unconnected Ports, Weddick
- Re: Unconnected Ports, Peter Alfke
  - Re: Unconnected Ports, Hal Murray
    - Re: Unconnected Ports, Mark McDougall
CMOS sensor stops aquring images.., CMOS
What is the definition of steering logic?, spammersarevermin
XC2000, mstrug
- Re: XC2000, Peter Alfke
  - Re: XC2000, GPE
    - Re: XC2000, Peter Alfke
    - Re: XC2000, Peter Alfke
- Message not available
  - Re: XC2000, Peter Alfke
    - Re: XC2000, Antti Lukats
    - Re: XC2000, Jim Granville
    - Re: XC2000, Antti Lukats
    - Re: XC2000, Peter Alfke
    - Re: XC2000, Antti Lukats
    - Re: XC2000, M.Randelzhofer
- Message not available
  - Re: XC2000, Dziadek
- re:XC2000, ralfsmith
Wishbone comments, Martin Schoeberl
- Re: Wishbone comments, Jon Beniston
- Re: Wishbone comments, Martin Schoeberl
  - Re: Wishbone comments, Martin Schoeberl
Xilinx DCM_ADV 280MHz no lock, Brad Smallridge
- Re: Xilinx DCM_ADV 280MHz no lock, Antti Lukats
- Re: Xilinx DCM_ADV 280MHz no lock, Avrum
  - Re: Xilinx DCM_ADV 280MHz no lock, Brad Smallridge
- Re: Xilinx DCM_ADV 280MHz no lock, Jochen
Bidirectional Bus, zora
- Re: Bidirectional Bus, Duane Clark
- re:Bidirectional Bus, zora
virtex II global buffer, zora
- Re: virtex II global buffer, Brannon
Support for runtime reconfiguration, cacosta
Design Implementation in Xilinx XST, Jeremy Wood
- Re: Design Implementation in Xilinx XST, Tim Good
  - Re: Design Implementation in Xilinx XST, Aurelian Lazarut
    - Re: Design Implementation in Xilinx XST, Jeremy Wood
  - Re: Design Implementation in Xilinx XST, Martin Schoeberl
We need to program several thousands Xilinx flashes XCF025..., zlyh
- Re: We need to program several thousands Xilinx flashes XCF025..., backhus
- Re: We need to program several thousands Xilinx flashes XCF025..., Hal Murray
- Chief decides to ask Xilinx, zlyh
XST vs Synplify, francesco_poderico
- Re: XST vs Synplify, amyler
- Re: XST vs Synplify, JustJohn
  - Re: XST vs Synplify, francesco_poderico
FPGA and metastability once again, v_mirgorodsky
- Re: FPGA and metastability once again, Peter Alfke
- Re: FPGA and metastability once again, Avrum
  - Re: FPGA and metastability once again, v_mirgorodsky
    - Re: FPGA and metastability once again, Avrum
- Re: FPGA and metastability once again, Philip Freidin
Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a, Nju Njoroge
- Re: Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a, Duane Clark
  - Re: Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a, Nju Njoroge
Question on 2048 point FFT( Basic), aj
- Re: Question on 2048 point FFT( Basic), backhus
Microblaze and custom peripherals, ssirowy@xxxxxxxxx
- Re: Microblaze and custom peripherals, John Williams
  - Re: Microblaze and custom peripherals, ssirowy@xxxxxxxxx
    - Re: Microblaze and custom peripherals, Göran Bilski
    - Re: Microblaze and custom peripherals, ssirowy@xxxxxxxxx
    - Re: Microblaze and custom peripherals, Göran Bilski
  - Re: Microblaze and custom peripherals, ssirowy@xxxxxxxxx
Flip-flop state extraction out of reaback stream in Virtex-II/Pro, heiko
- Re: Flip-flop state extraction out of reaback stream in Virtex-II/Pro, John Williams
  - Re: Flip-flop state extraction out of reaback stream in Virtex-II/Pro, heiko
    - Re: Flip-flop state extraction out of reaback stream in Virtex-II/Pro, heiko
Access to long lines in Virtex-II, heiko
- Re: Access to long lines in Virtex-II, Javier Castillo
Aurora over Rocket IO and EDk, beeraka@xxxxxxxxx
- Re: Aurora over Rocket IO and EDk, sjulhes
- Re: Aurora over Rocket IO and EDk, Duane Clark
data encryption standard, hirenshah.05@xxxxxxxxx
- Re: data encryption standard, Ray Andraka
  - Re: data encryption standard, hirenshah.05@xxxxxxxxx
    - Re: data encryption standard, Simon Peacock
Stupid reset question, Nick
- Re: Stupid reset question, Austin Lesea
  - Re: Stupid reset question, Nick
  - Re: Stupid reset question, Simon Peacock
- Re: Stupid reset question, Phil Hays
  - Message not available
    - Re: Stupid reset question, Phil Hays
  - Re: Stupid reset question, Nick
  - Re: Stupid reset question, Ray Andraka
    - Re: Stupid reset question, Phil Hays
    - Re: Stupid reset question, Ray Andraka
    - Re: Stupid reset question, Phil Hays
- Re: Stupid reset question, Johan Bernspång
Disabling Xilinx clock enable usage..., johnp
- Re: Disabling Xilinx clock enable usage..., allanherriman
  - Re: Disabling Xilinx clock enable usage..., allanherriman
- Re: Disabling Xilinx clock enable usage..., Antti Lukats
  - Re: Disabling Xilinx clock enable usage..., John_H
    - Re: Disabling Xilinx clock enable usage..., Antti Lukats
    - Re: Disabling Xilinx clock enable usage..., johnp
    - Re: Disabling Xilinx clock enable usage..., Duane Clark
    - Re: Disabling Xilinx clock enable usage..., JustJohn
    - Re: Disabling Xilinx clock enable usage..., allanherriman
    - Re: Disabling Xilinx clock enable usage..., johnp
    - Re: Disabling Xilinx clock enable usage..., Mike Treseler
Xst optimizes almost everything away, Adrian Knoth
- Re: Xst optimizes almost everything away, Andy Peters
  - Re: Xst optimizes almost everything away, Adrian Knoth
    - Re: Xst optimizes almost everything away, Mike Treseler
    - Re: Xst optimizes almost everything away, Andy Peters
    - Re: Xst optimizes almost everything away, Adrian Knoth
- Re: Xst optimizes almost everything away, JustJohn
  - Re: Xst optimizes almost everything away, Adrian Knoth
    - Re: Xst optimizes almost everything away, JustJohn
    - Re: Xst optimizes almost everything away, JustJohn
    - Re: Xst optimizes almost everything away, Adrian Knoth
Re: How do I find the datasheet of this device "TIOPA 690 3BZL9"?, Symon
- Re: How do I find the datasheet of this device "TIOPA 690 3BZL9"?, Simon Peacock
Patient Monitors: Reading RS232 output w/ an FPGA, Mark
- Re: Patient Monitors: Reading RS232 output w/ an FPGA, Kolja Sulimma
- Re: Patient Monitors: Reading RS232 output w/ an FPGA, Andy Peters
  - Re: Patient Monitors: Reading RS232 output w/ an FPGA, Duane Clark
- Re: Patient Monitors: Reading RS232 output w/ an FPGA, Mike Treseler
- Re: Patient Monitors: Reading RS232 output w/ an FPGA, Mark
Newbie: Problems with clocks, Andreas
- Re: Newbie: Problems with clocks, Andy Peters
  - Re: Newbie: Problems with clocks, Andreas
- Re: Newbie: Problems with clocks, backhus
  - Re: Newbie: Problems with clocks, Andreas
Quartus Problem, Manfred Balik
- Re: Quartus Problem, Noway2
- Re: Quartus Problem, Mark
- Re: Quartus Problem, Mike Treseler
- Re: Quartus Problem, Vaughn Betz
Uart core for a virtex-4, Andrew Lohbihler
- Re: Uart core for a virtex-4, fad
  - Re: Uart core for a virtex-4, Aurelian Lazarut
- Re: Uart core for a virtex-4, Brian Davis
  - Re: Uart core for a virtex-4, Andrew Lohbihler
architecture, nezhate
- Re: architecture, nezhate
  - Re: architecture, Simon Peacock
    - Re: architecture, nezhate
    - Re: architecture, Kolja Sulimma
JTAG read from xc18v04, james . knoll
XST options in XPS, brassaro@xxxxxxxxxxxxxxxx
- Re: XST options in XPS, Joseph Samson
  - Re: XST options in XPS, brassaro@xxxxxxxxxxxxxxxx
Reconfiguration Issue -- Pulse Program?, Stephen Craven
Sounds or other means to indicate end of compilation in Xilinx ISE, Fred
- Re: Sounds or other means to indicate end of compilation in Xilinx ISE, Mike Harrison
  - Re: Sounds or other means to indicate end of compilation in Xilinx ISE, Sean Durkin
- Re: Sounds or other means to indicate end of compilation in Xilinx ISE, Jan Panteltje
  - Re: Sounds or other means to indicate end of compilation in Xilinx ISE, Fred
    - Re: Sounds or other means to indicate end of compilation in Xilinx ISE, Gabor
    - Re: Sounds or other means to indicate end of compilation in Xilinx ISE, Simon Peacock
    - Re: Sounds or other means to indicate end of compilation in Xilinx ISE, jaxato
Modelsim Verification : Retain FSM state names, Georgios Sidiropoulos
- Re: Modelsim Verification : Retain FSM state names, ajeetha
- Re: Modelsim Verification : Retain FSM state names, Bob Perlman
  - Re: Modelsim Verification : Retain FSM state names, ajeetha
    - Re: Modelsim Verification : Retain FSM state names, Bob Perlman
    - Re: Modelsim Verification : Retain FSM state names, Brian Philofsky
- Re: Modelsim Verification : Retain FSM state names, Mike Treseler
FFT on an FPGA, satpreetsingh
- Re: FFT on an FPGA, Robin Bruce
- Re: FFT on an FPGA, Ray Andraka
- Re: FFT on an FPGA, JJ
using generated timing constraints, bgshea
- Re: using generated timing constraints, bgshea
CLK input DOES NOT use clk pin ( Altera Stratix II), huangjie
- Re: CLK input DOES NOT use clk pin ( Altera Stratix II), John Adair
  - Re: CLK input DOES NOT use clk pin ( Altera Stratix II), huangjie
- Re: CLK input DOES NOT use clk pin ( Altera Stratix II), JustJohn
  - Re: CLK input DOES NOT use clk pin ( Altera Stratix II), huangjie
    - Re: CLK input DOES NOT use clk pin ( Altera Stratix II), Simon Peacock
    - Re: CLK input DOES NOT use clk pin ( Altera Stratix II), huangjie
    - Re: CLK input DOES NOT use clk pin ( Altera Stratix II), Simon Peacock
    - Re: CLK input DOES NOT use clk pin ( Altera Stratix II), huangjie
    - Re: CLK input DOES NOT use clk pin ( Altera Stratix II), Simon Peacock
    - Re: CLK input DOES NOT use clk pin ( Altera Stratix II), huangjie
    - Re: CLK input DOES NOT use clk pin ( Altera Stratix II), Vaughn Betz
- Re: CLK input DOES NOT use clk pin ( Altera Stratix II), Vaughn Betz
Asynchronous design, Chintan
- Re: Asynchronous design, Tim Wescott
  - Re: Asynchronous design, Chintan
    - Re: Asynchronous design, PeteS
    - Re: Asynchronous design, PeteS
- Re: Asynchronous design, John Adair
- Re: Asynchronous design, PeteS
Assertion file update problem in ModeSim (via Tcl script), Alex
input in spartan kit(its urgent), ravindra kalla
- hi, ravindra kalla
  - Re: hi, Peter Alfke
Functional problems with Stratix II when configuring at higher temperatures?, henn_xxx@xxxxxxxxxxx
Oh no! Resets Again? Yes, but it could be important., JustJohn
- Re: Oh no! Resets Again? Yes, but it could be important., Raymund Hofmann
- Re: Oh no! Resets Again? Yes, but it could be important., allanherriman
  - Re: Oh no! Resets Again? Yes, but it could be important., JustJohn
    - Re: Oh no! Resets Again? Yes, but it could be important., allanherriman
    - Re: Oh no! Resets Again? Yes, but it could be important., JustJohn
    - Re: Oh no! Resets Again? Yes, but it could be important., allanherriman
- Re: Oh no! Resets Again? Yes, but it could be important., Duane Clark
- Re: Oh no! Resets Again? Yes, but it could be important., John_H
  - Re: Oh no! Resets Again? Yes, but it could be important., JustJohn
    - Re: Oh no! Resets Again? Yes, but it could be important., Mike Treseler
    - Re: Oh no! Resets Again? Yes, but it could be important., Hal Murray
    - Re: Oh no! Resets Again? Yes, but it could be important., Mike Treseler
    - Re: Oh no! Resets Again? Yes, but it could be important., JustJohn
    - Re: Oh no! Resets Again? Yes, but it could be important., Andy Peters
    - Re: Oh no! Resets Again? Yes, but it could be important., JustJohn
    - Re: Oh no! Resets Again? Yes, but it could be important., mk
    - Re: Oh no! Resets Again? Yes, but it could be important., Simon Peacock
    - Re: Oh no! Resets Again? Yes, but it could be important., Symon
    - Re: Oh no! Resets Again? Yes, but it could be important., langwadt
    - Re: Oh no! Resets Again? Yes, but it could be important., JustJohn
Help Needed Regarding VPR, vivekgarg330
- Re: Help Needed Regarding VPR, Vaughn Betz
Chipscope Pro License Problem, Andrew
- Re: Chipscope Pro License Problem, Mike Treseler
Virtex 4 FIFO16 blocks - Corruption ?, Sylvain Munaut
Xilinx routing details, motty
- Re: Xilinx routing details, Totally_Lost
Bidirectional bus control, Chintan
- Re: Bidirectional bus control, Alex
- Re: Bidirectional bus control, Andy Peters
synthesis, Abbs
- Re: synthesis, Noway2
  - Re: synthesis, Abbs
    - Re: synthesis, Noway2
    - Re: synthesis, Abbs
    - Re: synthesis, backhus
hi everyone, tell me something about Cyclone II., badgrant
- Re: hi everyone, tell me something about Cyclone II., amyler
- Re: hi everyone, tell me something about Cyclone II., amyler
- Re: hi everyone, tell me something about Cyclone II., Austin Lesea
  - Re: hi everyone, tell me something about Cyclone II., gallen
    - Re: hi everyone, tell me something about Cyclone II., austin
    - Re: hi everyone, tell me something about Cyclone II., gallen
- Re: hi everyone, tell me something about Cyclone II., Subroto Datta
FPGA Reconfiguration : Virtex-4 Frames, Andreas Nett
- Re: FPGA Reconfiguration : Virtex-4 Frames, Stephane
- Re: FPGA Reconfiguration : Virtex-4 Frames, Austin Lesea
  - Re: FPGA Reconfiguration : Virtex-4 Frames, Stephane
    - Re: FPGA Reconfiguration : Virtex-4 Frames, Austin Lesea
Setting the environment variable in ISE 7.1?, Andrew Lohbihler
- Re: Setting the environment variable in ISE 7.1?, francesco_poderico
  - Re: Setting the environment variable in ISE 7.1?, Gabor
    - Re: Setting the environment variable in ISE 7.1?, Andrew Lohbihler
    - Re: Setting the environment variable in ISE 7.1?, Brad Smallridge
    - Re: Setting the environment variable in ISE 7.1?, Brad Smallridge
    - Re: Setting the environment variable in ISE 7.1?, Brad Smallridge
Parallel Cable IV not detecting, aj
- Re: Parallel Cable IV not detecting, Andy Peters
  - Re: Parallel Cable IV not detecting, Zara
    - Re: Parallel Cable IV not detecting, Andy Peters
- Re: Parallel Cable IV not detecting, John Adair
  - Re: Parallel Cable IV not detecting, aj
aliases, balaji286@xxxxxxxxx
Xilinx clock IOB Place Error 645, Brad Smallridge
- Re: Xilinx clock IOB Place Error 645, Brad Smallridge
- Re: Xilinx clock IOB Place Error 645, Brad Smallridge
FPGA CAM/TCAM, tony.p.lee@xxxxxxxxx
- Re: FPGA CAM/TCAM, Mike Treseler
DCM corner issue, seb_tech_fr
- Re: DCM corner issue, Symon
  - Re: DCM corner issue, Austin Lesea
- Re: DCM corner issue, seb_tech_fr
  - Re: DCM corner issue, Austin Lesea
- Re: DCM corner issue, seb_tech_fr
Re: Error (XST): translate terminal to FCT (bis), Erwan
ml310 DDR problem, Stephen Craven
- Re: ml310 DDR problem, John Williams
Trying to define Opendrain Outputs, ALuPin@xxxxxx
- Re: Trying to define Opendrain Outputs, ALuPin@xxxxxx
  - Re: Trying to define Opendrain Outputs, Nicolas Matringe
    - Re: Trying to define Opendrain Outputs, ALuPin@xxxxxx
    - Re: Trying to define Opendrain Outputs, Simon Peacock
    - Re: Trying to define Opendrain Outputs, Andy Peters
Suggestions on good books, Michael Chan
- Re: Suggestions on good books, fad
- Re: Suggestions on good books, Austin Lesea
- Re: Suggestions on good books, Gunter Knittel
  - Re: Suggestions on good books, Bob Perlman
    - Re: Suggestions on good books, Gunter Knittel
- Re: Suggestions on good books, Bob Perlman
  - Re: Suggestions on good books, Michael Chan
UART CORE FOR NIOS, lesnleung
- Re: UART CORE FOR NIOS, Tim Wescott
- Re: UART CORE FOR NIOS, Mark McDougall
- Re: UART CORE FOR NIOS, htoerrin
Data recovery (XAPP224), prav
- Re: Data recovery (XAPP224), John_H
- re:Data recovery (XAPP224), calaf
Cyclone II and Stratix II dual ports are dead, altera_smells
- Re: Cyclone II and Stratix II dual ports are dead, altera_smells
ml300 LCD question, Eric Yeh
xst synthesis, brassaro@xxxxxxxxxxxxxxxx
- Re: xst synthesis, brassaro@xxxxxxxxxxxxxxxx
  - Re: xst synthesis, Andrew Lohbihler
    - Re: xst synthesis, brassaro@xxxxxxxxxxxxxxxx
    - Re: xst synthesis, brassaro@xxxxxxxxxxxxxxxx
Lattice XP flash memory access....., r . kinkead
- Re: Lattice XP flash memory access....., Gabor
  - Re: Lattice XP flash memory access....., r . kinkead
complexity of arithmetic, adnan . aziz
- Re: complexity of arithmetic, Totally_Lost
- Re: complexity of arithmetic, Gabor
- Re: complexity of arithmetic, Mike Treseler
Quartus crash, Martin Schoeberl
- Re: Quartus crash, Subroto Datta
  - Re: Quartus crash, Martin Schoeberl
Raggedstone1, MINI-CAN - Low Cost Carriage, John Adair
- Re: Raggedstone1, MINI-CAN - Low Cost Carriage, Mike Harrison
  - Re: Raggedstone1, MINI-CAN - Low Cost Carriage, John Adair
ISE 6.2i strange behavior, sjulhes
- Re: ISE 6.2i strange behavior, Andrew Lohbihler
- Re: ISE 6.2i strange behavior, Newman
- Re: ISE 6.2i strange behavior, sjulhes
XILINX BlockRAM setuphold violation (setup) problems HELP!, Heiner Litz
- Re: XILINX BlockRAM setuphold violation (setup) problems HELP!, Peter Alfke
Multiple Waits 2 Xilinx WebPack???, rules
- Re: Multiple Waits 2 Xilinx WebPack???, Kunal Shenoy
- Re: Multiple Waits 2 Xilinx WebPack???, Avrum
ISE SP4 installer on Linux, aholtzma
- Re: ISE SP4 installer on Linux, Adrian Knoth
  - Re: ISE SP4 installer on Linux, Eric Smith
    - Re: ISE SP4 installer on Linux, Adrian Knoth
3 devices on the same external bus, calaf
- Re: 3 devices on the same external bus, PeteS
- re:3 devices on the same external bus, calaf
Rise time/fall time for Spartan3 clock inputs, abeaujean@xxxxxxxxxxxxx
- Re: Rise time/fall time for Spartan3 clock inputs, Gabor
  - Re: Rise time/fall time for Spartan3 clock inputs, abeaujean@xxxxxxxxxxxxx
- Re: Rise time/fall time for Spartan3 clock inputs, Peter Alfke
  - Re: Rise time/fall time for Spartan3 clock inputs, abeaujean@xxxxxxxxxxxxx
    - Re: Rise time/fall time for Spartan3 clock inputs, Peter Alfke
- Message not available
  - Re: Rise time/fall time for Spartan3 clock inputs, abeaujean@xxxxxxxxxxxxx
    - Re: Rise time/fall time for Spartan3 clock inputs, Jim Granville
    - Re: Rise time/fall time for Spartan3 clock inputs, johnp
Research Position, Gunter Knittel
- Message not available
  - Re: Research Position, Gunter Knittel
Multiple instantiation in SystemC, Moises
RoHS, Martin
- Re: RoHS, Benjamin Todd
  - Re: RoHS, PeteS
    - Re: RoHS, allanherriman
    - Re: RoHS, PeteS
    - Re: RoHS, Martin
    - Re: RoHS, Mike Harrison
    - Re: RoHS, Martin
    - Re: RoHS, Jim Granville
    - Re: RoHS, Martin
    - Re: RoHS, Jon Elson
    - Re: RoHS, dp
    - Re: RoHS, Rene Tschaggelar
    - Re: RoHS, news
- Re: RoHS, Rene Tschaggelar
Using JTAG cable for general comms, nchandra@xxxxxxxxx
- Re: Using JTAG cable for general comms, derek
Having trouble Detecting ethernet packets using ethereal, ashwin
- Re: Having trouble Detecting ethernet packets using ethereal, Arlet
  - Message not available
    - Re: Having trouble Detecting ethernet packets using ethereal, Simon Peacock
- Re: Having trouble Detecting ethernet packets using ethereal, Rene Tschaggelar
  - Re: Having trouble Detecting ethernet packets using ethereal, Aurelian Lazarut
  - Re: Having trouble Detecting ethernet packets using ethereal, Mike Treseler
64/65-octet encapsulation IP cores?, rem
Xilinx flip-chip PCB processing, AmyS
- Re: Xilinx flip-chip PCB processing, Austin Lesea
Re: Power on problem--- signal behaving strangely, Andy Peters
downloading with XMD ?, sjulhes
- Re: downloading with XMD ?, Newman
  - Re: downloading with XMD ?, sjulhes
  - Re: downloading with XMD ?, tony.p.lee@xxxxxxxxx
    - Re: downloading with XMD ?, Ray Andraka
    - Re: downloading with XMD ?, Newman
    - Re: downloading with XMD ?, Peter Ryser
Help needed to design recursive digital circuit, PiyushG
- Re: Help needed to design recursive digital circuit, backhus
Re: ISE, JTAG and ChipScopePro., Antti Lukats
- Re: ISE, JTAG and ChipScopePro., GaLaKtIkUs?
  - Re: ISE, JTAG and ChipScopePro., fad
PC networking through modems, CMOS
- Re: PC networking through modems, dp
i2c slave does not acknowlege, CMOS
- Re: i2c slave does not acknowlege, allanherriman
- Message not available
  - Re: i2c slave does not acknowlege, Jeremy Stringer
    - Re: i2c slave does not acknowlege, CMOS
    - Re: i2c slave does not acknowlege, Nicolas Matringe
Viretx4 FX chip availability, Paul R
- Re: Viretx4 FX chip availability, Antti Lukats
- Re: Viretx4 FX chip availability, Alex Gibson
- Re: Viretx4 FX chip availability, Jon Beniston
  - Re: Viretx4 FX chip availability, Antti Lukats
    - Re: Viretx4 FX chip availability, Jon Beniston
- Re: Viretx4 FX chip availability, Paul R
  - Re: Viretx4 FX chip availability, Symon
Bitstream compression, Martin
- Re: Bitstream compression, allanherriman
  - Re: Bitstream compression, Martin
    - Re: Bitstream compression, Antonio Pasini
- Re: Bitstream compression, Martin
AVNET's Spartan3 400 dev board & PCI, Krzysztof Przednowek
- Re: AVNET's Spartan3 400 dev board & PCI, John Adair
  - Re: AVNET's Spartan3 400 dev board & PCI, Kolja Sulimma
- Re: AVNET's Spartan3 400 dev board & PCI, Antti Lukats
  - Re: AVNET's Spartan3 400 dev board & PCI, Krzysztof Przednowek
    - Re: AVNET's Spartan3 400 dev board & PCI, Sylvain Munaut
Kingston ValueRAM double deckers, Jonathan Schneider
- Re: Kingston ValueRAM double deckers, Hal Murray
- Re: Kingston ValueRAM double deckers, Simon Peacock
Re: Difficulty compiling on Quartus 2 version 5, Subroto Datta
- Re: Difficulty compiling on Quartus 2 version 5, altras
  - Re: Difficulty compiling on Quartus 2 version 5, Mike Treseler
ModelSim XE III: Arrow disapears during single-stepping, Udo
Add files to Xilinx ISE Project w/script, sharpa17@xxxxxxxxx
- Re: Add files to Xilinx ISE Project w/script, Duane Clark
  - Re: Add files to Xilinx ISE Project w/script, Jim Wu
  - Re: Add files to Xilinx ISE Project w/script, Rick North
    - Re: Add files to Xilinx ISE Project w/script, Marc Randolph
- Re: Add files to Xilinx ISE Project w/script, Gabor
- Re: Add files to Xilinx ISE Project w/script, Phil Hays
  - Re: Add files to Xilinx ISE Project w/script, Petter Gustad
  - Re: Add files to Xilinx ISE Project w/script, Andrew
    - Re: Add files to Xilinx ISE Project w/script, Phil Hays
    - Re: Add files to Xilinx ISE Project w/script, John Williams
FPGA KIT recommendation, Jordi
- Re: FPGA KIT recommendation, Antti Lukats
- Re: FPGA KIT recommendation, Stephen Craven
  - Re: FPGA KIT recommendation, Eli Hughes
- Message not available
  - Re: FPGA KIT recommendation, Jordi
    - Re: FPGA KIT recommendation, JASH
MicroBlaze Seminar UK, John Adair
Re: fastest possible USB, Mike Harrison
- <Possible follow-ups>
- Re: fastest possible USB, John Adair
  - Re: fastest possible USB, Simon Peacock
- Re: fastest possible USB, Steven Derrien
  - Re: fastest possible USB, johnp
- Re: fastest possible USB, Hal Murray
Clock signal for an external peripheral, Marco
- Message not available
  - Message not available
    - Re: Clock signal for an external peripheral, Simon Peacock
    - Re: Clock signal for an external peripheral, Marco
Re: SDRAM controller., Ray Andraka
- Re: SDRAM controller., jai.dhar@xxxxxxxxx
Is this even true???, Subhasri krishnan
- Re: Is this even true???, Bob Perlman
- Re: Is this even true???, air_bits
- Re: Is this even true???, Kryten
  - Re: Is this even true???, air_bits
    - Re: Is this even true???, Subhasri krishnan
    - Re: Is this even true???, air_bits
- Message not available
  - Re: Is this even true???, Kryten
Signal timing problem, motty
- Re: Signal timing problem, Mike Treseler
  - Re: Signal timing problem, motty
    - Re: Signal timing problem, Andy Peters
    - Re: Signal timing problem, motty
    - Re: Signal timing problem, Mike Treseler
- Re: Signal timing problem, Kunal Shenoy
Can't pack into OLOGIC, john
- Re: Can't pack into OLOGIC, Aurelian Lazarut
  - Re: Can't pack into OLOGIC, john
- Re: Can't pack into OLOGIC, fastgreen2000
  - Re: Can't pack into OLOGIC, fastgreen2000
    - Re: Can't pack into OLOGIC, john
    - Re: Can't pack into OLOGIC, Symon
    - Re: Can't pack into OLOGIC, john
- Re: Can't pack into OLOGIC, john
  - Re: Can't pack into OLOGIC, Joseph Samson
- Re: Can't pack into OLOGIC, Brian Davis
  - Re: Can't pack into OLOGIC, john
    - Re: Can't pack into OLOGIC, Brian Davis
open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, g.wall
- Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Eli Hughes
  - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, jvdh
  - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Jan Panteltje
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Eli Hughes
- Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, air_bits
  - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, air_bits
- Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Mike Treseler
  - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, air_bits
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Mike Treseler
  - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Eric Smith
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, air_bits
    - Message not available
    - Message not available
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, air_bits
    - Message not available
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, air_bits
    - Message not available
    - Message not available
    - Message not available
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Jim Granville
    - Message not available
    - Message not available
    - Message not available
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Jim Granville
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, air_bits
    - Message not available
    - Message not available
    - Message not available
    - Message not available
    - Message not available
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Mike Treseler
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Kim Enkovaara
  - Message not available
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Bob Perlman
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Totally_Lost
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, fjh-mailbox-38@xxxxxxxxxx
    - Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm, Simon Peacock
fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors, g.wall
- Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors, Peter Alfke
  - Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors, Tim Wescott
- Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors, Stephen Craven
  - Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors, g.wall
- Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors, air_bits
  - Message not available
    - Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors, air_bits
Looking for tutorials for bootloader writing on xilinx SOC ??, sjulhes
- Re: Looking for tutorials for bootloader writing on xilinx SOC ??, Marco
  - Re: Looking for tutorials for bootloader writing on xilinx SOC ??, sjulhes
Coolrunner output pins stuck at 0V, jvdh
- Re: Coolrunner output pins stuck at 0V, Gabor
  - Re: Coolrunner output pins stuck at 0V, jvdh
    - Re: Coolrunner output pins stuck at 0V, jvdh
    - Message not available
    - Re: Coolrunner output pins stuck at 0V, jvdh
Spartan 3e is slower than Virtex 2p, Alan Nishioka
- Re: Spartan 3e is slower than Virtex 2p, Martin Thompson
- Re: Spartan 3e is slower than Virtex 2p, John Adair
Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?, Phil Hays
- <Possible follow-ups>
- Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?, Kunal Shenoy
  - Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?, Frank
    - Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?, Kunal Shenoy
- Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?, Peter Alfke
- Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?, backhus
  - Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?, Symon
    - Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?, backhus
- Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?, Kolja Sulimma
- Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?, Kolja Sulimma
Rocket IO reset problem, Jdon
- Re: Rocket IO reset problem, mengsoo
Xilinx Block RAM - initializing with Intel Hex-File, Udo
- Re: Xilinx Block RAM - initializing with Intel Hex-File, Symon
Best Case Timing Parameters, Ajay
- Re: Best Case Timing Parameters, Peter Alfke
  - Re: Best Case Timing Parameters, Bob Perlman
    - Re: Best Case Timing Parameters, Peter Alfke
  - Re: Best Case Timing Parameters, Jim Granville
- Re: Best Case Timing Parameters, Russ Panneton
How do i detect ethernet frames of layer 2 using ethereal?, ashwin
- Re: How do i detect ethernet frames of layer 2 using ethereal?, amyler
- Message not available
  - Re: How do i detect ethernet frames of layer 2 using ethereal?, Andrew Holme
    - Re: How do i detect ethernet frames of layer 2 using ethereal?, jai.dhar@xxxxxxxxx
Re: Installing FPGA Advantage on Linux machine, Mike Treseler
- <Possible follow-ups>
- Re: Installing FPGA Advantage on Linux machine, Hans
EDK 7.1, Virtex4 GPIO PULLIP problem, Antti Lukats
Forcing carry-ripple adder ?, Sylvain Munaut
- Re: Forcing carry-ripple adder ?, Symon
  - Re: Forcing carry-ripple adder ?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
    - Re: Forcing carry-ripple adder ?, Symon
    - Re: Forcing carry-ripple adder ?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
    - Re: Forcing carry-ripple adder ?, vssumesh
- Re: Forcing carry-ripple adder ?, Ray Andraka
  - Re: Forcing carry-ripple adder ?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
how to implement Fast Fourier Transform on virtex pro, aj
- Re: how to implement Fast Fourier Transform on virtex pro, Ray Andraka
- re:how to implement Fast Fourier Transform on virtex pro, seb_tech_fr
pci ml310 board, Nitesh
- Re: pci ml310 board, Peter Ryser
- Re: pci ml310 board, beeraka@xxxxxxxxx
  - Re: pci ml310 board, Peter Ryser
ERROR:Pack:1564: ML403 & Xilinx Platform Studio 7.1.02i, Udo
Re: Wirelength information from Xilinx ISE 6.1, John_H
Re: PC Core AD(x) I/O Enable?, Kevin Brace
Need some help with interfacing spartan III to a computer..., Dhivya
- Re: Need some help with interfacing spartan III to a computer..., Robert
- Re: Need some help with interfacing spartan III to a computer..., M.Randelzhofer
- Re: Need some help with interfacing spartan III to a computer..., derek
What are important factors when selecting Intellectual Property?, k e
- Re: What are important factors when selecting Intellectual Property?, Hal Murray
  - Re: What are important factors when selecting Intellectual Property?, Jeremy Stringer
Bus for Spartan3, Marco
- Re: Bus for Spartan3, Antti Lukats
  - Re: Bus for Spartan3, Jeremy Stringer
- Re: Bus for Spartan3, Antonio Pasini
  - Re: Bus for Spartan3, Marco
old xilinx components, Vanheesbeke Stefaan
- Re: old xilinx components, Antti Lukats
- Re: old xilinx components, Philip Freidin
  - Re: old xilinx components, Vanheesbeke Stefaan
    - Re: old xilinx components, Jon Elson
- Re: old xilinx components, DerekSimmons@xxxxxxxxxxxxxxx
Internal signal to drive clock resources, aydin3w
- Re: Internal signal to drive clock resources, Gabor
  - Re: Internal signal to drive clock resources, vssumesh
8x8-bit multiply, WTec
- Re: 8x8-bit multiply, Bevan Weiss
how to use registers and fifo in ipif, Athena
- Re: how to use registers and fifo in ipif, Athena
Re: What does the IP in IPCORE stand for?, allanherriman
- Re: What does the IP in IPCORE stand for?, mughat
  - Re: What does the IP in IPCORE stand for?, Bevan Weiss
  - Re: What does the IP in IPCORE stand for? (say "gateware" instead), Adam Megacz
    - Re: What does the IP in IPCORE stand for? (say "gateware" instead), Symon
To create an IPCORE, rha_x
- Re: To create an IPCORE, Kevin Brace
Suggestions/Recommendations with CPLD's and Software, Henry
- Re: Suggestions/Recommendations with CPLD's and Software, Michael Schuster
- Re: Suggestions/Recommendations with CPLD's and Software, Noway2
  - Message not available
    - Re: Suggestions/Recommendations with CPLD's and Software, Noway2
    - Re: Suggestions/Recommendations with CPLD's and Software, dale . prather
- Re: Suggestions/Recommendations with CPLD's and Software, M.Randelzhofer
- Re: Suggestions/Recommendations with CPLD's and Software, dale . prather
- Re: Suggestions/Recommendations with CPLD's and Software, Jon Elson
Delay insertion in Xilinx Verilog, Dave Roberts
- Re: Delay insertion in Xilinx Verilog, robertncsu
  - Re: Delay insertion in Xilinx Verilog, Dave Roberts
    - Re: Delay insertion in Xilinx Verilog, Hal Murray
    - Re: Delay insertion in Xilinx Verilog, Zara
    - Re: Delay insertion in Xilinx Verilog, Gabor
Easy Xilinx Platform Studio Question, Brad Smallridge
- Re: Easy Xilinx Platform Studio Question, Kunal Shenoy
  - Re: Easy Xilinx Platform Studio Question, Brad Smallridge
    - Re: Easy Xilinx Platform Studio Question, Kunal Shenoy
    - Re: Easy Xilinx Platform Studio Question, Brad Smallridge
- Re: Easy Xilinx Platform Studio Question, Zara
  - Re: Easy Xilinx Platform Studio Question, Brad Smallridge
looking for FPGA pin header board, Terradestroyer
- Re: looking for FPGA pin header board, Hal Murray
  - Re: looking for FPGA pin header board, robertncsu
    - Re: looking for FPGA pin header board, busonerd
    - Re: looking for FPGA pin header board, Terradestroyer
    - Re: looking for FPGA pin header board, Simon Peacock
- Re: looking for FPGA pin header board, Uwe Bonnes
ISE 8.1 news--BaseX going away, but WebPack gains devices and features, Eric Smith
- Re: ISE 8.1 news--BaseX going away, but WebPack gains devices and features, Simon Peacock
  - Re: ISE 8.1 news--BaseX going away, but WebPack gains devices and features, John McCluskey
Verilog Editor., Eli Hughes
- Re: Verilog Editor., Jan Panteltje
  - Re: Verilog Editor., Eli Hughes
    - Re: Verilog Editor., Jan Panteltje
    - Re: Verilog Editor., jussij
    - Re: Verilog Editor., Ron
    - Re: Verilog Editor., jussij
    - Re: Verilog Editor., Andy Peters
    - Re: Verilog Editor., jussij
    - Re: Verilog Editor., johnp
    - Re: Verilog Editor., electro
- Message not available
  - Re: Verilog Editor., robertncsu
- Re: Verilog Editor., Simon Peacock
- Message not available
  - Re: Verilog Editor., jussij
    - Re: Verilog Editor., Bob Perlman
    - Re: Verilog Editor., Simon Peacock
    - Re: Verilog Editor., jussij
ML402 DDR SDRAM, Jered
XILINX ISE 7.1 Symbol Editor, Udo
What does @ mean in EDIF?, myusenetacct
how to map kernel element of FFT to VIRTEX Pro Board, aj
- Re: how to map kernel element of FFT to VIRTEX Pro Board, Stephen Craven
VHDL algorithm/code for implementing QAM on FPGA, Tony Acquah
BRAMs readback, giohdl@xxxxxxxxxxxx
- Re: BRAMs readback, Antti Lukats
- Re: BRAMs readback, rha_x
  - Re: BRAMs readback, Ray Andraka
- Re: BRAMs readback, JASH
- Re: BRAMs readback, derek
Xilinx Package/Logic Options, Eli Hughes
- Re: Xilinx Package/Logic Options, Antti Lukats
  - Re: Xilinx Package/Logic Options, PeteS
  - Re: Xilinx Package/Logic Options, Hal Murray
    - Re: Xilinx Package/Logic Options, Ray Andraka
Malloc on PowerPC on VirtexII pro, Tibo
- Re: Malloc on PowerPC on VirtexII pro, Alan Nishioka
- Re: Malloc on PowerPC on VirtexII pro, Peter Ryser
Re: PCI test bench, Kim Enkovaara
- <Possible follow-ups>
- Re: PCI test bench, Mark McDougall
- Re: PCI test bench, Andy Peters
Spartan3 bus for DSP, Marco
Re: 24 to 32 8-bit PWM outputs, David R Brooks
which Altera CPLD?, Manfred Balik
- Re: which Altera CPLD?, Daniel Lang
Adder synthesis, nezhate
- Re: Adder synthesis, backhus
- Re: Adder synthesis, John_H
- Re: Adder synthesis, Philip Freidin
  - Re: Adder synthesis, Hal Murray
The Xilinx MultiPoint Synthesis Flow - Synplify Pro, irezki
xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine, yusufilker
- Re: xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine, Hal Murray
  - Re: xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine, yusufilker
- Re: xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine, francesco_poderico
- Re: xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine, Peter Ryser
USB host, Mich
Why Spartan-3e is the best, Antti Lukats
- Re: Why Spartan-3e is the best, Falk Brunner
  - Re: Why Spartan-3e is the best, Antti Lukats
- Re: Why Spartan-3e is the best, Jecel
  - Re: Why Spartan-3e is the best, Jim Granville
    - Re: Why Spartan-3e is the best, Antti Lukats
    - Re: Why Spartan-3e is the best, Tobias Weingartner
    - Message not available
    - Re: Why Spartan-3e is the best, Tobias Weingartner
    - Message not available
    - Message not available
    - Re: Why Spartan-3e is the best, Tobias Weingartner
    - Re: Why Spartan-3e is the best, Eric Smith
    - Message not available
    - Re: Why Spartan-3e is the best, langwadt
    - Re: Why Spartan-3e is the best, Bevan Weiss
    - Re: Why Spartan-3e is the best, Symon
    - Re: Why Spartan-3e is the best, Jecel
Anybody understand this ISE 7.1 error, and what to do about it???, Andrew Lohbihler
- Re: Anybody understand this ISE 7.1 error, and what to do about it???, Antti Lukats
- Re: Anybody understand this ISE 7.1 error, and what to do about it???, John_H
  - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Andrew Lohbihler
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, John_H
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Ray Andraka
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Andrew Lohbihler
  - Re: Anybody understand this ISE 7.1 error, and what to do about it???, GaLaKtIkUs?
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Sylvain Munaut
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Simon Peacock
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, GaLaKtIkUs?
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Andrew Lohbihler
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Antti Lukats
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Mike Treseler
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Sylvain Munaut
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Mike Treseler
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, John_H
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Andrew Lohbihler
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Ray Andraka
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Andrew Lohbihler
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Ray Andraka
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Antti Lukats
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Ray Andraka
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Simon Peacock
    - Message not available
    - Re: Anybody understand this ISE 7.1 error, and what to do about it???, Simon Peacock
icarus verilog, GaLaKtIkUs?
- Re: icarus verilog, Eli Hughes
  - Re: icarus verilog, Jan Panteltje
    - Re: icarus verilog, Kevin Brace
    - Re: icarus verilog, panteltje
    - Re: icarus verilog, gallen
    - Re: icarus verilog, Andy Peters
    - Re: icarus verilog, David Brown
    - Re: icarus verilog, Jan Panteltje
  - Re: icarus verilog, Brian Dam Pedersen
    - Re: icarus verilog, Uwe Bonnes
    - Re: icarus verilog, Jan Panteltje
    - Re: icarus verilog, google
    - Re: icarus verilog, Phil Tomson
    - Re: icarus verilog, Uwe Bonnes
    - Re: icarus verilog, panteltje
- Re: icarus verilog -- look here ..., air_bits
ChipScope and Spartan-3 Starter Kit (DO-SPAR3-DK), GaLaKtIkUs?
- Re: ChipScope and Spartan-3 Starter Kit (DO-SPAR3-DK), Eli Hughes
  - Re: ChipScope and Spartan-3 Starter Kit (DO-SPAR3-DK), GaLaKtIkUs?
    - Re: ChipScope and Spartan-3 Starter Kit (DO-SPAR3-DK), Eli Hughes
- Re: ChipScope and Spartan-3 Starter Kit (DO-SPAR3-DK), Robert
Clock J4, johngalil
- Re: Clock J4, johngalil
use ppc405 on virtex-II pro, Eric
- Re: use ppc405 on virtex-II pro, Nitro
- Re: use ppc405 on virtex-II pro, Matthieu Michon
- Re: use ppc405 on virtex-II pro, beeraka@xxxxxxxxx
Actel SoftARM IP core generator tools finally available !!!, Antti Lukats
- Re: Actel SoftARM IP core generator tools finally available !!!, Eli Hughes
Memec Insight Spartan-3 LC Development Kit USB drivers needed! Help!, Robert
- Re: Memec Insight Spartan-3 LC Development Kit USB drivers needed! Help!, Antti Lukats
  - Re: Memec Insight Spartan-3 LC Development Kit USB drivers needed! Help!, Robert
    - Re: Memec Insight Spartan-3 LC Development Kit USB drivers needed! Help!, Antti Lukats
    - Re: Memec Insight Spartan-3 LC Development Kit USB drivers needed! Help!, Robert
- Re: Memec Insight Spartan-3 LC Development Kit USB drivers needed! Help!, Alex Gibson
I have received a job offer, Marco
- Re: I have received a job offer, Bo
  - Re: I have received a job offer, Marco
    - Re: I have received a job offer, learnfpga
    - Re: I have received a job offer, Peter Alfke
    - Re: I have received a job offer, Marco
    - Re: I have received a job offer, Luis Vaccaro
    - Re: I have received a job offer, Luis Vaccaro
XC2VP125, Robin Bruce
- Re: XC2VP125, Stephen Craven
  - Re: XC2VP125, Robin Bruce
Using inout ports in VHDL, ncunha
- Re: Using inout ports in VHDL, Symon
- Re: Using inout ports in VHDL, anupam
- re:Using inout ports in VHDL, gkirilov
LWIP on microblaze socket limit to 2, kdfake@xxxxxxxx
using Spartan3 DCM in ActiveHDL, krby_xtrm
Xilinx trouble opening ml40x_emb_ref_xx, Brad Smallridge
- Re: Xilinx trouble opening ml40x_emb_ref_xx, Newman
  - Re: Xilinx trouble opening ml40x_emb_ref_xx, Jim Granville
    - Re: Xilinx trouble opening ml40x_emb_ref_xx, Jim Granville
  - Re: Xilinx trouble opening ml40x_emb_ref_xx, Brad Smallridge
crc code using vhdl found , few questions on it!!!, ashwin
Re: FPGA : PCI core needed, Kevin Brace
- <Possible follow-ups>
- Re: FPGA : PCI core needed, Kevin Brace
- Re: FPGA : PCI core needed, Kevin Brace
- FPGA : PCI core needed, Kevin Brace
  - Re: FPGA : PCI core needed, Eric Smith
    - Re: FPGA : PCI core needed, Kevin Brace
    - Re: FPGA : PCI core needed, Mike Treseler
Newbie. Clocks., mice
- Re: Newbie. Clocks., Brian Dam Pedersen
- Re: Newbie. Clocks., Symon
  - Re: Newbie. Clocks., Symon
    - Re: Newbie. Clocks., Bob Perlman
- Re: Newbie. Clocks., Kunal Shenoy
- Re: Newbie. Clocks., Andy Peters
- re:Newbie. Clocks., mice
clock detection, seb_tech_fr
- Re: clock detection, Jochen
- Re: clock detection, Peter Alfke
  - Re: clock detection, Simon Peacock
- Re: clock detection, Ben G
- Re: clock detection, seb_tech_fr
  - Re: clock detection, Ben G
FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
- Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Rene Tschaggelar
  - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Eric Smith
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Jim Granville
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Martin Ellis
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Jim Granville
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Robin Bruce
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Martin Ellis
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Martin Ellis
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Benjamin Ylvisaker
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Robin Bruce
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Thomas Reinemann
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Robin Bruce
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Andy Peters
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Robin Bruce
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Jim Granville
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Robin Bruce
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Jim Granville
    - Message not available
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Message not available
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Robin Bruce
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Mike Treseler
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Robin Bruce
    - The HLL GUI multi-fpga DIME design environment, air_bits
    - Re: The HLL GUI multi-fpga DIME design environment, Mike Treseler
    - Re: The HLL GUI multi-fpga DIME design environment, air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Martin Ellis
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Message not available
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Eric Smith
    - Message not available
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Kolja Sulimma
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Kolja Sulimma
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Jeremy Stringer
    - Message not available
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Phil Tomson
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Rene Tschaggelar
  - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), c d saunter
- Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Jan Panteltje
  - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Eric Smith
    - Message not available
    - Message not available
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Eric Smith
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
    - Message not available
    - Message not available
    - Message not available
    - Message not available
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Robin Bruce
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), Jeremy Stringer
- Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
  - Message not available
    - Re: FPGA C Compiler on sourceforge.net (TMCC derivative), air_bits
ChipScope on ML401 kit, raybakk
- Re: ChipScope on ML401 kit, raybakk
differential clock in EDK, Johan Bernspång
- Re: differential clock in EDK, Antti Lukats
  - Re: differential clock in EDK, Johan Bernspång
- Re: differential clock in EDK, Zara
- Re: differential clock in EDK, Eli Hughes
- Re: differential clock in EDK, Paul Hartke
  - Re: differential clock in EDK, Johan Bernspång
FPGA : PCI-CORE, bijoy
- Re: FPGA : PCI-CORE, I. Ulises Hernandez
  - Re: FPGA : PCI-CORE, bijoy
    - Re: FPGA : PCI-CORE, Antti Lukats
    - Re: FPGA : PCI-CORE, Nial Stewart
    - Re: FPGA : PCI-CORE, Antti Lukats
    - Re: FPGA : PCI-CORE, Ram
    - Re: FPGA : PCI-CORE, Antti Lukats
- Re: FPGA : PCI-CORE, John_H
  - Re: FPGA : PCI-CORE, Antti Lukats
    - Re: FPGA : PCI-CORE, John_H
    - Re: FPGA : PCI-CORE, Kevin Brace
    - Re: FPGA : PCI-CORE, John_H
    - Re: FPGA : PCI-CORE, Kevin Brace
    - Re: FPGA : PCI-CORE, Duane Clark
    - Re: FPGA : PCI-CORE, Philip Freidin
- Re: FPGA : PCI-CORE, Kevin Brace
Spartan IIE VHDL inout port bidirectional bus problem., liaobojie
- Re: Spartan IIE VHDL inout port bidirectional bus problem., Zara
Re: newbie question, Jeremy Stringer
- Re: newbie question, Udo
Re: ISE 8.1, EDK 8.1 any pre-release info available?, Ray Andraka
can ethereal detect an ethernet packet for which crc is wrong, ashwin
- Re: can ethereal detect an ethernet packet for which crc is wrong, zcsizmadia@xxxxxxxxx
  - Re: can ethereal detect an ethernet packet for which crc is wrong, Hal Murray
- Re: can ethereal detect an ethernet packet for which crc is wrong, Mike Treseler
- Re: can ethereal detect an ethernet packet for which crc is wrong, Gavin
  - lenght/type not included, ashwin
    - Re: lenght/type not included, Gavin
  - Re: can ethereal detect an ethernet packet for which crc is wrong, Jeremy Stringer
- Re: can ethereal detect an ethernet packet for which crc is wrong, Hal Murray
- Re: can ethereal detect an ethernet packet for which crc is wrong, I. Ulises Hernandez
Virtex4 temperature-sensing feature... does it work?, I. Ulises Hernandez
- Re: Virtex4 temperature-sensing feature... does it work?, Chris
- Message not available
  - Re: Virtex4 temperature-sensing feature... does it work?, I. Ulises Hernandez
Xilinx V2P Speed Grades, Simon Heinzle
Thank-you Xilinx!, Eli Hughes
- Re: Thank-you Xilinx!, Antti Lukats
Re: Simulating Cyclone II PLL, Subroto Datta
- <Possible follow-ups>
- Re: Simulating Cyclone II PLL, ALuPin
Re: System ACE equivalent for CPLDs, dp
Xilinx ML403 Error 1 LED, kdfake@xxxxxxxx
- Re: Xilinx ML403 Error 1 LED, Newman
- <Possible follow-ups>
- Re: Xilinx ML403 Error 1 LED, kdfake@xxxxxxxx
  - Re: Xilinx ML403 Error 1 LED, Peter Ryser
Re: Cost to go from FPGA to ASIC, Kunal
question on sw tools for xilnx FPGA, ppirrip
- Re: question on sw tools for xilnx FPGA, Kunal
  - Re: question on sw tools for xilnx FPGA, Antti Lukats
Re: hex rep. in VHDL, Mark McDougall
- Re: hex rep. in VHDL, Mike Treseler
  - Re: hex rep. in VHDL, Mark McDougall
    - Re: hex rep. in VHDL, Jonathan Bromley
    - Message not available
    - Re: hex rep. in VHDL, Mark McDougall
Re: Sigma-Delta A/D, langwadt
- <Possible follow-ups>
- Re: Sigma-Delta A/D, John Monro
  - Message not available
    - Re: Sigma-Delta A/D, Ray Andraka
    - Re: Sigma-Delta A/D, langwadt
  - Message not available
    - Re: Sigma-Delta A/D, John Monro
Quartus II Simulation, morpheus
- Message not available
  - Re: Quartus II Simulation, morpheus
Re: Spartan-3E starter kit, Peter Alfke
- Re: Spartan-3E starter kit, Antti Lukats
  - Message not available
    - Re: Spartan-3E starter kit, Eli Hughes
  - Message not available
    - Re: Spartan-3E starter kit, Antti Lukats
    - Message not available
    - Message not available
    - Re: Antti's Logic Assembler ( was Spartan-3E starter kit ), Jim Granville
- <Possible follow-ups>
- Re: Spartan-3E starter kit, setup
- Re: Spartan-3E starter kit, Peter Alfke
  - Re: Spartan-3E starter kit, Pratip Mukherjee
  - Re: Spartan-3E starter kit, Brian Davis
    - Re: Spartan-3E starter kit, Peter Alfke
    - Re: Spartan-3E starter kit, Uwe Bonnes
    - Re: Spartan-3E starter kit, Antti Lukats
    - Re: Spartan-3E starter kit, Brian Davis
  - Message not available
    - Re: Spartan-3E starter kit, GPE
  - Re: Spartan-3E starter kit, Jim Granville
    - Re: Spartan-3E starter kit, Peter Alfke
    - Re: Spartan-3E starter kit, Jim Granville
    - Re: Spartan-3E starter kit, Eli Hughes
    - Re: Spartan-3E starter kit, Peter Alfke
    - Message not available
    - Re: Spartan-3E starter kit, Peter Alfke
Re: SystemACE parts wanted, Ed McGettigan
- Re: SystemACE parts wanted, Antti Lukats
  - Re: SystemACE parts wanted, Eli Hughes
    - Re: SystemACE parts wanted, Antti Lukats