Re: 24 to 32 8-bit PWM outputs



Emtech wrote:
This is for an RGB LED demo display application.

1. There will be mixing of colours done at say 3ms intervals for
>    each colour to stay ithin the 10ms and take avantage of
>    persistance of vision.
2. Bits accuracy in the duty cycle is not very important since
> the PWM is only for brightness control.
3. The outputs must at least be synchronized to the colour mixing
>    intervals, i.e. 3ms intervals.  In other words, the PWM will
>    further divide the 3ms intervals to control brightness.
4. These will only be used in an RGB LED display application
> hence the only real importance is the 10ms refresh limit.

Thank you for your input.

Very interesting. Earlier this year I did a PWM design to control RGB LEDs for a medical testing device. The client wanted a total of 61 RGB LEDs, or 183 channels of PWM output, with 16-bit resolution and 1 ms refresh period (Yes, this means a 65.536 MHz clock). I divided this up into three Xilinx Spartan-3 FPGAs with 63 PWM output channels each in order to avoid BGA packages and simplify the overall PCB layout. Each FPGA drives 20 or 21 RGB LED chips.

IIRC, it didn't quite fit into an XC3S50, so we ended up using
the XC3S200. A design with less resolution or fewer channels
would easily fit into the smaller chip.

The PWM hardware is driven entirely by the contents of a single
block RAM, and uses one of the RAM's ports to read out the data.
This gives a great deal of flexibility as to how the system
controller gets the intensity values into the RAM via its other
port, using anything from a conventional parallel bus interface
to a synchronous or asynchronous serial interface.

-- Dave Tweed
.



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