Re: Avoiding meta stability? No where in this thread...

On Wed, 05 Oct 2005 21:31:02 -0700, austin <austin@xxxxxxxxxx> wrote:
>Oops,

Damn! I thought I had said enough, but apparently not.

>Looks like I read the 'english', and not the code.

Both are correct. Paul's circuit is a shift register (2 bits) and
it is logically indistinguishable from a shift register.

>Looks like it is registered once, and then sent to another FF. Both
>FF's are clocked on the rising edge, so it is not a metastability
>"filter"

Excuse me, this is a two stage synchronizer. Exactly.

>(which would clock the second FF on the falling edge) to reduce the
>probability of a metastable event

Which is NOT a two stage synchronizer. The "clock it on the falling edge"
circuit saves 1/2 a cycle in synchronizer latency, and makes
a major sacrifice in resolving time. This is not a good synchronizer.

Go read http://www.fpga-faq.org/FAQ_Pages/0017_Tell_me_about_metastables.htm

for more on this poor circuit.


>(they can not be prevented, but the statistics can be improved to where
>you just don't care).

Well I agree with this.

>That is a standard looking shift register. No issue with that.

Right. And assuming that it is clocked on the global clock net
(no reason not to assume this given Paul's posting) there are no
hold time issues that you seem to be worried about (probably because
it is written as a shift register (which can be problematic in ASICs)).

>The FPGA fabric is always slower than a global clock (except in some
>rare cases where things are really poorly placed due to other issues
>with poor or confusing or conflicting constraints), so there is no
>problem (like there could be in an ASIC) that the data might get to some
>FF's before the clock would (and an event is missed altogether).
>
>The tools should make a reasonably good placement to prevent problems.
>
>I have seen where folks used location constraints to be sure that the
>clock arrived at the MSB or last stage first, and then went against the
>flow of data towards the LSB or first stage to ensure that the clock
>would always get to the FF BEFORE the data coming to the FF could
>possibly change in ASIC standard cell flows. Not really needed in an
>FPGA: the fabric and clocks are supposed to be "correct by
>construction" so the engineer doesn't have to worry.

Agreed, but the issue being discussed in synchronizers.

>This whole thing also has nothing to do with metastability.

Oh yes it does! A two bit shift register is identical to a two
stage synchronizer.

>Austin


>> Paul Marciano wrote:
>>>
>>> Peter, rookie question: given the following synchronizer:
>>>
>>> module test(input clk, input in_sig, output reg out_sig);
>>> reg [1:0] ss;
>>>
>>> always @(posedge clk)
>>> begin
>>> out_sig <= ss[1];
>>> ss <= { ss[0], in_sig };
>>> end
>>> endmodule
>>>
>>>
>>> How, specifically, do I tell XST to locate ss[1] as close as possible
>>> to ss[0]?
>>>
>>>
>>> Regards,
>>> Paul.
>>>

Great! Now I've pissed of Peter and Austin. Did I mention I'm
not having a great week :-) :-)

Philip Freidin
Crusader for understanding metastability and how to minimize it.




===================
Philip Freidin
philip.freidin@xxxxxxxxxxxx
Host for WWW.FPGA-FAQ.ORG
.

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