High Load
Hallo,
I have made a clock divider using a counter connected to master clock and a
comparator.
The comparator has a clock enable to avoid "gating-clock".
Now my trouble. I have connected some logic blocks to the new clock, but in
this way it has high load and delay.
The warning message:
WARNING:Route - CLK
Net:opb_spi_adc_dac_0/opb_spi_adc_dac_0/USER_LOGIC_I/clk_spi
may have excessive skew because 3 NON-CLK pins
failed to route using a CLK template.
This peripheral is a part of a small micrcontroller based on microblaze.
What could I do to solve this trouble?
Many Thanks in advance
Marco
.
Relevant Pages
- Re: Problem with simple VHDL piece of code
... to use an explicit reset of some kind. ... behind "counter" by one clock cycle. ... comparator is now trivial, and involves no arithmetic. ... A smart synthesizer might do a reachability analysis on the counter, ...
(comp.lang.vhdl) - Re: need fast FPGA suggestions
... and clock the output I/O blocks with the 250MHz clock ... in DDR mode. ... If they need finer resolution, then there are ways to fudge that with the DDR. ... you think a 13-bit counter feeding a 13-bit identity comparator will work at 250 MHz? ...
(comp.arch.fpga) - Re: Problem with simple VHDL piece of code
... I'm sure the input signals are correct... ... to use an explicit reset of some kind. ... behind "counter" by one clock cycle. ... comparator is now trivial, and involves no arithmetic. ...
(comp.lang.vhdl) - Re: LMH7220 docs
... into an FPGA as a clock. ... The National LMH7220 keeps popping up in searches. ... but I wonder if anyone has a better suggestion? ... "comparator", ...
(sci.electronics.design) - Re: How to count pulses per second ?
... transistors, or a few transistors and a comparator, or a single chip ... second (so you need another clock) and something to say that it's got enough ... You'll have hysteresis, if you don't want your comparator oscillating, ...
(sci.electronics.design) |
|
