comp.arch.fpga

• Date Index

---

• Re: Integrator, Tim Wescott
• [xst]:clk information question, Tim Verstraete
• Memory usage and ISE, Hans
  • Re: Memory usage and ISE, Alvin Andries
• Re: SystemACE parts wanted, Antti Lukats
  • Re: SystemACE parts wanted, Eli Hughes
    • Re: SystemACE parts wanted, Antti Lukats
• array type implementable in ISE?, Jack
  • Re: array type implementable in ISE?, Kolja Sulimma
• Re: Xilinx Microblaze prefill icache, Zara
• Re: ISE 8.1, EDK 8.1 any pre-release info available?, Jim Granville
• Spartan3 DFS & DLL Behaviour, Raymund Hofmann
• Xilinx ML403 Virtex 4 IIC uses bitbang test?, Newman
• Re: Semi-OT: LVDS and Cold Sparing, TC
• Spartan-3E starter kit, Pratip Mukherjee
  • Re: Spartan-3E starter kit, Peter Alfke
    • Message not available
      • Re: Spartan-3E starter kit, Mike Harrison
      • Re: Spartan-3E starter kit, Peter Alfke
      • Re: Spartan-3E starter kit, Simon Peacock
      • Re: Spartan-3E starter kit, Gavin
      • Message not available
      • Re: Spartan-3E starter kit, Eli Hughes
• How to reduse the logic., himassk
  • Re: How to reduse the logic., Kunal
  • Re: How to reduse the logic., backhus
• xilinx design reuse netlist format, James Bond
  • Re: xilinx design reuse netlist format, Jerome
    • Re: xilinx design reuse netlist format, James Bond
• Virtex-4: SLICEM and SLICEL, why? (Peter Alfke?), Udo
  • Re: Virtex-4: SLICEM and SLICEL, why? (Peter Alfke?), Peter Alfke
    • Re: Virtex-4: SLICEM and SLICEL, why? (Peter Alfke?), Udo
      • Re: Virtex-4: SLICEM and SLICEL, why? (Peter Alfke?), Kunal
• Reed Solomon generation / verification, atarynka
• Virtex-4 DSP48 - special features (Peter Alfke?), Udo
  • Re: Virtex-4 DSP48 - special features (Peter Alfke?), comcast
  • Re: Virtex-4 DSP48 - special features (Peter Alfke?), Peter Alfke
• ethernet phy- DP83847, ashwin
  • Re: ethernet phy- DP83847, Gavin
• Mitrion-C, Robin Bruce
• Sigma-Delta A/D, Marco
  • Re: Sigma-Delta A/D, Symon
    • Re: Sigma-Delta A/D, Marco
    • Re: Sigma-Delta A/D, Marco
      • Re: Sigma-Delta A/D, langwadt
      • Re: Sigma-Delta A/D, John Monro
      • Re: Sigma-Delta A/D, Marco
      • Re: Sigma-Delta A/D, John Monro
      • Re: Sigma-Delta A/D, Marco
      • Re: Sigma-Delta A/D, Jim Granville
      • Re: Sigma-Delta A/D, Marco
      • Re: Sigma-Delta A/D, Marco
  • Re: Sigma-Delta A/D, Kolja Sulimma
• hex rep. in VHDL, anupam
  • Re: hex rep. in VHDL, Mark McDougall
    • Re: hex rep. in VHDL, anupam
      • Re: hex rep. in VHDL, Falk Brunner
      • Re: hex rep. in VHDL, ajeetha
  • re:hex rep. in VHDL, gkirilov
• locking hdl to a particular fpga, Matthew Plante
  • Re: locking hdl to a particular fpga, Antti Lukats
  • Re: locking hdl to a particular fpga, Phil Hays
    • Re: locking hdl to a particular fpga, raulizahi@xxxxxxxxx
• another FPGA/asic vendor dead :(, Antti Lukats
  • Re: another FPGA/asic vendor dead :(, Jim Granville
    • Re: another FPGA/asic vendor dead :(, Antti Lukats
      • Re: another FPGA/asic vendor dead :(, Jim Granville
      • Re: another FPGA/asic vendor dead :(, Antti Lukats
      • Re: another FPGA/asic vendor dead :(, Jim Granville
  • Re: another FPGA/asic vendor dead :(, Hal Murray
    • Re: another FPGA/asic vendor dead :(, Jim Granville
  • Re: another FPGA/asic vendor dead :(, Philip Freidin
    • Re: another FPGA/asic vendor dead :(, Joel Kolstad
      • Re: another FPGA/asic vendor dead :(, Philip Freidin
• ASIC HDL coding styles, v_mirgorodsky
  • Message not available
    • Message not available
      • Re: ASIC HDL coding styles, v_mirgorodsky
  • <Possible follow-ups>
  • ASIC HDL coding styles, v_mirgorodsky
• Cost to go from FPGA to ASIC, Bob
  • Re: Cost to go from FPGA to ASIC, Kunal
    • Re: Cost to go from FPGA to ASIC, Bob
      • Re: Cost to go from FPGA to ASIC, Hans
      • Re: Cost to go from FPGA to ASIC, Bob
      • Re: Cost to go from FPGA to ASIC, Ben Twijnstra
    • Re: Cost to go from FPGA to ASIC, Antti Lukats
      • Re: Cost to go from FPGA to ASIC, Austin Lesea
      • Re: Cost to go from FPGA to ASIC, Paul Marciano
      • Re: Cost to go from FPGA to ASIC, Austin Lesea
      • Message not available
      • Re: Cost to go from FPGA to ASIC, Austin Lesea
      • Re: Cost to go from FPGA to ASIC, Jim Granville
      • Re: Cost to go from FPGA to ASIC, Antti Lukats
  • Re: Cost to go from FPGA to ASIC, Jon Beniston
    • Re: Cost to go from FPGA to ASIC, Austin Lesea
  • Re: Cost to go from FPGA to ASIC, JJ
    • Re: Cost to go from FPGA to ASIC, Peter Alfke
• Anyone know hwicap?, robin
• Optimizing a State Machine, gkirilov
  • Re: Optimizing a State Machine, Peter Alfke
  • re:Optimizing a State Machine, gkirilov
  • Message not available
    • Message not available
      • Message not available
      • Re: Optimizing a State Machine, Ben Twijnstra
• crc on only data or including the address, ashwin
  • Re: crc on only data or including the address, Mike Treseler
    • Re: crc on only data or including the address, Sylvain Munaut
  • Re: crc on only data or including the address, Philip Freidin
• Re: Microblaze & Memory DMA operation, Terry Fowler
  • <Possible follow-ups>
  • Re: Microblaze & Memory DMA operation, Terry Fowler
• state machine with 2 clock's, dimon1977
  • Message not available
    • Message not available
      • Re: state machine with 2 clock's, John_H
  • Message not available
    • Message not available
      • Re: state machine with 2 clock's, Ray Andraka
      • Re: state machine with 2 clock's, Peter Alfke
• Re: SDRAM in EDK, Antti Lukats
  • Re: SDRAM in EDK, mvetromille
  • Re: SDRAM in EDK, Ray Andraka
  • <Possible follow-ups>
  • re:SDRAM in EDK, gkirilov
• Physical interface for PCI express(PIPE) electrical information, sudarangareddy
  • Re: Physical interface for PCI express(PIPE) electrical information, PeteS
  • Re: Physical interface for PCI express(PIPE) electrical information, PeteS
• cic filter, zhl_gs1980
  • Re: cic filter, Symon
• newbie question, ppirrip
  • Re: newbie question, backhus
• 7.1i on Linux installation saga, Eric Smith
  • Re: 7.1i on Linux installation saga, Steven J. Hill
• ETHERNET MAC, ashwin
  • Re: ETHERNET MAC, Mike Treseler
  • Re: ETHERNET MAC, I. Ulises Hernandez
    • Re: ETHERNET MAC, jai.dhar@xxxxxxxxx
• Anyone have experience with Linux in V2Pro?, Austin Franklin
  • Re: Anyone have experience with Linux in V2Pro?, Antti Lukats
  • Re: Anyone have experience with Linux in V2Pro?, beeraka@xxxxxxxxx
• EDK custom IP read/write, Eric
  • Re: EDK custom IP read/write, Eric
• Xilinx FIFO Generator: FIFO Length, Nemesis
  • Re: Xilinx FIFO Generator: FIFO Length, Peter Alfke
    • Re: Xilinx FIFO Generator: FIFO Length, Nemesis
      • Re: Xilinx FIFO Generator: FIFO Length, Robert
      • Re: Xilinx FIFO Generator: FIFO Length, Nemesis
      • Re: Xilinx FIFO Generator: FIFO Length, Peter Alfke
      • Message not available
      • Re: Xilinx FIFO Generator: FIFO Length, Nemesis
      • Message not available
      • Re: Xilinx FIFO Generator: FIFO Length, Hal Murray
• Re: xpower : logic power=0, Brendan Cullen
  • Re: xpower : logic power=0, Pasacco
    • Re: xpower : logic power=0, Brendan Cullen
• Re: OSD implementation in FPGA, Zara
  • Message not available
    • Re: OSD implementation in FPGA, Zara
      • Message not available
      • Re: OSD implementation in FPGA, Ray Andraka
      • Re: OSD implementation in FPGA, Antonio Pasini
• System ACE equivalent for CPLDs, Benjamin Todd
  • Re: System ACE equivalent for CPLDs, Neil Glenn Jacobson
    • Re: System ACE equivalent for CPLDs, Benjamin Todd
      • Re: System ACE equivalent for CPLDs, Neil Glenn Jacobson
      • Re: System ACE equivalent for CPLDs, Benjamin Todd
      • Re: System ACE equivalent for CPLDs, dp
      • Re: System ACE equivalent for CPLDs, Neil Glenn Jacobson
      • Re: System ACE equivalent for CPLDs, dp
• Xilinx ISERDES, Brad Smallridge
  • Re: Xilinx ISERDES, unfrostedpoptart
    • Re: Xilinx ISERDES, Peter Alfke
      • Re: Xilinx ISERDES, Brad Smallridge
      • Re: Xilinx ISERDES, Peter Alfke
      • Message not available
      • Re: Xilinx ISERDES, Kolja Sulimma
      • Re: Xilinx ISERDES, Brad Smallridge
      • Re: Xilinx ISERDES, Joseph Samson
      • Re: Xilinx ISERDES, Brad Smallridge
      • Re: Xilinx ISERDES, Joseph Samson
• Xilinx ML403 Many warnings, Brad Smallridge
  • Re: Xilinx ML403 Many warnings, Kunal
    • Re: Xilinx ML403 Many warnings, Brad Smallridge
      • Re: Xilinx ML403 Many warnings, Antti Lukats
• a few questions, Gert Baars
  • Re: a few questions, Phil Hays
  • Re: a few questions, Jan Panteltje
  • Re: a few questions, Phil Hays
    • Re: a few questions, Gert Baars
      • Re: a few questions, Tim Wescott
      • Re: a few questions, Phil Hays
      • Re: a few questions, Ben Twijnstra
      • Re: a few questions, Dave
      • Re: a few questions, chris_ivan
  • Re: a few questions, Gary Pace
    • Re: a few questions, fpgabuilder
    • Re: a few questions, fpgabuilder
      • Re: a few questions, Phil Hays
      • Re: a few questions, fpgabuilder
      • Re: a few questions, Jan Panteltje
      • Re: a few questions, fpgabuilder
      • Re: a few questions, Mike Treseler
      • Re: a few questions, Len
      • Re: a few questions, chris_ivan
      • Re: a few questions, Len
      • Re: a few questions, Tim Wescott
• verilog code, hirenshah.05@xxxxxxxxx
  • Re: verilog code, JJ
  • Re: verilog code, John_H
    • Re: verilog code, fpgabuilder
• XC3S4000 pricing?, Dom Gilligan
  • Re: XC3S4000 pricing?, Simon Peacock
• Doubt in using CD22M3494, praveen . kantharajapura
  • Re: Doubt in using CD22M3494, alan
• 24 to 32 8-bit PWM outputs, Emtech
  • Re: 24 to 32 8-bit PWM outputs, Antti Lukats
  • Re: 24 to 32 8-bit PWM outputs, Mike Harrison
  • Re: 24 to 32 8-bit PWM outputs, David Brooks
    • Re: 24 to 32 8-bit PWM outputs, Emtech
      • Re: 24 to 32 8-bit PWM outputs, Peter Alfke
      • Re: 24 to 32 8-bit PWM outputs, Jim Granville
      • Re: 24 to 32 8-bit PWM outputs, David Tweed
  • Re: 24 to 32 8-bit PWM outputs, Ulf Samuelsson
• SoC Processor design at gate level for edu, raph
  • Re: SoC Processor design at gate level for edu, Antti Lukats
    • Re: SoC Processor design at gate level for edu, Kunal
  • Re: SoC Processor design at gate level for edu, Jim Granville
  • Re: SoC Processor design at gate level for edu, Simon Peacock
  • Message not available
    • Re: SoC Processor design at gate level for edu, Kryten
• RS232 Uart for Virtex-II Pro, Eric
  • Re: RS232 Uart for Virtex-II Pro, Javier Castillo
  • Re: RS232 Uart for Virtex-II Pro, Ray Andraka
    • Re: RS232 Uart for Virtex-II Pro, young
• FPGA Design Docs, se
  • Re: FPGA Design Docs, Mike Treseler
    • Re: FPGA Design Docs, Nial Stewart
      • Re: FPGA Design Docs, Mike Treseler
• write on a DG834GT modem, toon
• Re: Simulation : EDK, grupy
• Re: clock frequency after RTL synthesis vs PAR, Marc Randolph
  • Re: clock frequency after RTL synthesis vs PAR, Pasacco
    • Re: clock frequency after RTL synthesis vs PAR, Marc Randolph
    • Re: clock frequency after RTL synthesis vs PAR, Kunal
• .dat to .bit, Subhasri krishnan
  • Re: .dat to .bit, David Brooks
  • Re: .dat to .bit, devb
    • Re: .dat to .bit, Jan Panteltje
• Internal Loading in Spartan3, motty
• Coregen Memory Initialization (.coe file format), Robert
• RISC pipelining question, bobrics
• netgen port renaming, wa11
• ML401, GaLaKtIkUs?
  • Re: ML401, GaLaKtIkUs?
  • Re: ML401, Brad Smallridge
• low power design and unused i/os, fpgabuilder
  • Re: low power design and unused i/os, Peter Alfke
    • Message not available
      • Re: low power design and unused i/os, fpgabuilder
      • Re: low power design and unused i/os, Kolja Sulimma
      • Re: low power design and unused i/os, fpgabuilder
• "Cannot synthesize logic..." ERROR, bobrics
  • Re: "Cannot synthesize logic..." ERROR, bobrics
  • Re: "Cannot synthesize logic..." ERROR, unfrostedpoptart
    • Re: "Cannot synthesize logic..." ERROR, Bevan Weiss
    • Re: "Cannot synthesize logic..." ERROR, bobrics
    • Re: "Cannot synthesize logic..." ERROR, bobrics
• RPM reference for xilinx, Rick North
  • Re: RPM reference for xilinx, Ray Andraka
    • Re: RPM reference for xilinx, Rick North
      • Re: RPM reference for xilinx, Ray Andraka
• Re: Avnet Technical Support Terrible!!!, Brad Smallridge
  • Re: Avnet Technical Support Terrible!!!, Waage
    • Re: Avnet Technical Support Terrible!!!, Kunal
      • Re: Avnet Technical Support Terrible!!!, Waage
      • Re: Avnet Technical Support Terrible!!!, Antti Lukats
      • Re: Avnet Technical Support Terrible!!!, john . orlando
      • Re: Avnet Technical Support Terrible!!!, Antti Lukats
      • Re: Avnet Technical Support Terrible!!!, Waage
      • Re: Avnet Technical Support Terrible!!!, Gavin
      • Re: Avnet Technical Support Terrible!!!, Waage
      • Re: Avnet Technical Support Terrible!!!, Waage
• EDK on Virtex4 FX using embedded ethernet MAC, Pete
  • Re: EDK on Virtex4 FX using embedded ethernet MAC, Eric Smith
    • Re: EDK on Virtex4 FX using embedded ethernet MAC, Jon Beniston
  • Re: EDK on Virtex4 FX using embedded ethernet MAC, francesco_poderico
• C source for Spartan-3 with microblaze soft core for RS-232 comm, james . r . lamb
  • Re: C source for Spartan-3 with microblaze soft core for RS-232 comm, Marco
• EDK/ISE : unroutable design, Lionel Damez
  • Re: EDK/ISE : unroutable design, Mike Treseler
  • Re: EDK/ISE : unroutable design, Lionel Damez
    • Re: EDK/ISE : unroutable design, Mike Lewis
      • Re: EDK/ISE : unroutable design, Kolja Sulimma
      • Re: EDK/ISE : unroutable design, Paul Hartke
  • Re: EDK/ISE : unroutable design, Lionel Damez
• Re: how to connect my IP-Core to Microblaze in EDK and ISE with IPIF, moleo
• to write the driver for my own ip core, Athena
  • Re: to write the driver for my own ip core, Johan Bernspång
    • Message not available
      • Re: to write the driver for my own ip core, Kunal
  • Re: to write the driver for my own ip core, Athena
    • Re: to write the driver for my own ip core, Paul Hartke
• Re: MAC Architectures, Austin Lesea
• Spartn 3 configuration failure, nithin . pal
  • Re: Spartn 3 configuration failure, Benjamin Todd
  • Re: Spartn 3 configuration failure, bijoy
• Re: dagen.exe,where can i get it,thanks(for digital filter), cecarrion1
• which is Low power FPGA?, himassk
  • Re: which is Low power FPGA?, jerzy.gbur@xxxxxxxxx
    • Re: which is Low power FPGA?, Antti Lukats
      • Re: which is Low power FPGA?, jerzy.gbur@xxxxxxxxx
  • Re: which is Low power FPGA?, himassk
    • Re: which is Low power FPGA?, Jim Granville
      • Re: which is Low power FPGA?, Peter Alfke
      • Re: which is Low power FPGA?, luc
      • Re: which is Low power FPGA?, Jim Granville
  • Re: which is Low power FPGA?, Ray Andraka
  • Re: which is Low power FPGA?, Teo
• Implementation of 1024 point FFT in Actel FPGA, cisivakumar
  • Re: Implementation of 1024 point FFT in Actel FPGA, Thomas Womack
  • Re: Implementation of 1024 point FFT in Actel FPGA, Jon Elson
  • Re: Implementation of 1024 point FFT in Actel FPGA, Brijesh
• How to speed up the critical path (Xilinx), starbugs
  • Re: How to speed up the critical path (Xilinx), starbugs
  • Re: How to speed up the critical path (Xilinx), Zara
    • Re: How to speed up the critical path (Xilinx), zqhpnp@xxxxxxxxx
  • Re: How to speed up the critical path (Xilinx), Symon
  • Re: How to speed up the critical path (Xilinx), Eric DELAGE
• Webpack install yields "299" error, Eboy
• Xilinx USB cable, GaLaKtIkUs?
  • Re: Xilinx USB cable, John_H
    • Re: Xilinx USB cable, Antti Lukats
      • Re: Xilinx USB cable, John_H
      • Re: Xilinx USB cable, Antti Lukats
      • Re: Xilinx USB cable, Sean Durkin
  • Re: Xilinx USB cable, GaLaKtIkUs?
    • Re: Xilinx USB cable, John_H
• gast division carry chain usage, Brannon
• Anyone used the Xilinx' floating point core?, Simon Heinzle
  • Re: Anyone used the Xilinx' floating point core?, Brannon
    • Re: Anyone used the Xilinx' floating point core?, Simon Heinzle
• Carry Chain Design, Brannon
  • Re: Carry Chain Design, John_H
    • Re: Carry Chain Design, Brannon
      • Re: Carry Chain Design, Gabor
      • Re: Carry Chain Design, John_H
      • Re: Carry Chain Design, Brannon
• Simple PWM Spartan 3, fecs2
  • Re: Simple PWM Spartan 3, Eric Smith
  • Re: Simple PWM Spartan 3, Bevan Weiss
  • Re: Simple PWM Spartan 3, Peter Alfke
• Newbie question: XC3S400 Gate Count, jerryzy
  • Re: Newbie question: XC3S400 Gate Count, Ed McGettigan
    • Re: Newbie question: XC3S400 Gate Count, Paul Marciano
      • Re: Newbie question: XC3S400 Gate Count, Ed McGettigan
      • Re: Newbie question: XC3S400 Gate Count, Philip Freidin
    • Re: Newbie question: XC3S400 Gate Count, jerryzy
      • Re: Newbie question: XC3S400 Gate Count, Austin Lesea
      • Re: Newbie question: XC3S400 Gate Count, Ed McGettigan
• Program FPGA from PowerPC in V2P, Eric
  • Re: Program FPGA from PowerPC in V2P, alan
    • Re: Program FPGA from PowerPC in V2P, Eric
    • Re: Program FPGA from PowerPC in V2P, Kunal
• clock timing, Benjamin Menküc
  • Re: clock timing, Peter Alfke
    • Message not available
      • Re: clock timing, Antti Lukats
      • Re: clock timing, Benjamin Menküc
  • Re: clock timing, Symon
    • Re: clock timing, Benjamin Menküc
      • Re: clock timing, langwadt
      • Re: clock timing, Benjamin Menküc
      • Re: clock timing, Symon
      • Re: clock timing, Benjamin Menküc
      • Re: clock timing, Symon
      • Re: clock timing, Benjamin Menküc
      • Re: clock timing, Benjamin Menküc
  • Re: clock timing, Benjamin Menküc
• FPGA timming, Kunal
  • Re: FPGA timming, Kunal
    • Re: FPGA timming, Jeremy Stringer
    • Re: FPGA timming, Symon
    • Re: FPGA timming, Symon
      • Re: FPGA timming, Luke
      • Re: FPGA timming, Symon
      • Re: FPGA timming, Symon
      • Re: FPGA timming, Kunal
• Data2Mem usage - help required, Robert
  • Re: Data2Mem usage - help required, backhus
    • Re: Data2Mem usage - help required, Robert
      • Re: Data2Mem usage - help required, Jan Panteltje
    • Re: Data2Mem usage - help required, Robert
      • Re: Data2Mem usage - help required, backhus
• Rosetta Results, Austin Lesea
  • Re: Rosetta Results, francesco_poderico
    • Re: Rosetta Results, Austin Lesea
  • Re: Rosetta Results, Martin Thompson
    • Re: Rosetta Results, Austin Lesea
      • Re: Rosetta Results, Martin Thompson
      • Re: Rosetta Results, Austin Lesea
      • Re: Rosetta Results, Kolja Sulimma
      • Re: Rosetta Results, Austin Lesea
      • Re: Rosetta Results, Kolja Sulimma
• using i2c core, CMOS
  • Re: using i2c core, Symon
    • Re: using i2c core, CMOS
      • Re: using i2c core, Bevan Weiss
      • Re: using i2c core, CMOS
      • Re: using i2c core, John_H
      • Re: using i2c core, CMOS
      • Re: using i2c core, Bevan Weiss
      • Re: using i2c core, Bevan Weiss
      • Re: using i2c core, CMOS
      • Re: using i2c core, John_H
      • Re: using i2c core, CMOS
      • Re: using i2c core, John_H
      • Re: using i2c core, CMOS
      • Re: using i2c core, John_H
      • Re: using i2c core, CMOS
      • Re: using i2c core, John_H
      • Re: using i2c core, CMOS
      • Re: using i2c core, c d saunter
• XChecker cable and chipscope, GaLaKtIkUs?
  • Re: XChecker cable and chipscope, Antti Lukats
• chipscope pro problem, CMOS
• ADC implementation on fpga? Information and procudures wanted., pingboypulsar<spamoff>@hotmail.com
  • Re: ADC implementation on fpga? Information and procudures wanted., Peter Alfke
    • Re: ADC implementation on fpga? Information and procudures wanted., pingboypulsar<spamoff>@hotmail.com
      • Re: ADC implementation on fpga? Information and procudures wanted., Jim Granville
      • Re: ADC implementation on fpga? Information and procudures wanted., pingboypulsar<spamoff>@hotmail.com
      • Re: ADC implementation on fpga? Information and procudures wanted., Bevan Weiss
      • Re: ADC implementation on fpga? Information and procudures wanted., pingboypulsar<spamoff>@hotmail.com
      • Re: ADC implementation on fpga? Information and procudures wanted., Jonathan Bromley
      • Re: ADC implementation on fpga? Information and procudures wanted., pingboypulsar<spamoff>@hotmail.com
      • Re: ADC implementation on fpga? Information and procudures wanted., Jonathan Bromley
      • Re: ADC implementation on fpga? Information and procudures wanted., Phil Hays
      • Re: ADC implementation on fpga? Information and procudures wanted., Philip Freidin
      • Re: ADC implementation on fpga? Information and procudures wanted., Jonathan Bromley
      • Re: ADC implementation on fpga? Information and procudures wanted., Jim Granville
  • re:ADC implementation on fpga? Information and procudures wante, shorty
  • Re: ADC implementation on fpga? Information and procudures wanted., Brannon
• LSI RAPIDCHIP, Jerry
  • Re: LSI RAPIDCHIP, Alvin Andries
    • Re: LSI RAPIDCHIP, John B
      • Re: LSI RAPIDCHIP, John B
      • Re: LSI RAPIDCHIP, Jerry
  • <Possible follow-ups>
  • LSI RapidChip, John B
    • Re: LSI RapidChip, Jerry
• Re: Best Async FIFO Implementation, Jim Granville
  • Re: Best Async FIFO Implementation, Peter Alfke
  • <Possible follow-ups>
  • Re: Best Async FIFO Implementation, Jim Granville
    • Message not available
      • Re: Best Async FIFO Implementation, Jim Granville
    • Re: Best Async FIFO Implementation, Peter Alfke
      • Re: Best Async FIFO Implementation, Jim Granville
      • Re: Best Async FIFO Implementation, Peter Alfke
      • Message not available
      • Re: Best Async FIFO Implementation, Peter Alfke
      • Re: Best Async FIFO Implementation, Alex Shot
      • Re: Best Async FIFO Implementation, Robin Bruce
• Error (XST): translate terminal to FCT, Pasacco
• Low-cost, high-quality design team, DigitalSignal
• Implementing I2C master, Giox
  • Re: Implementing I2C master, PeteS
• About with Synplify Pro?, seabrench
  • Re: About with Synplify Pro?, Philip Freidin
• Mixed voltage in JTAG chain., Subhasri krishnan
  • Re: Mixed voltage in JTAG chain., PeteS
  • Re: Mixed voltage in JTAG chain., John Adair
• 3.3v<->5V, David Geirsson
  • Re: 3.3v<->5V, Slurp
  • Re: 3.3v<->5V, John Adair
    • Re: 3.3v<->5V, John Larkin
      • Re: 3.3v<->5V, GPE
      • Re: 3.3v<->5V, John Larkin
      • Re: 3.3v<->5V, John Adair
  • Re: 3.3v<->5V, Kolja Sulimma
• Implementing five stage pipeline, vssumesh
  • Re: Implementing five stage pipeline, vssumesh
  • Re: Implementing five stage pipeline, JJ
    • Re: Implementing five stage pipeline, vssumesh
    • Re: Implementing five stage pipeline, gallen
      • Re: Implementing five stage pipeline, JJ
      • Re: Implementing five stage pipeline, gallen
      • Re: Implementing five stage pipeline, JJ
      • Re: Implementing five stage pipeline, Stephen Craven
      • Re: Implementing five stage pipeline, JJ
      • Re: Implementing five stage pipeline, Martin Thompson
      • Re: Implementing five stage pipeline, JJ
  • Re: Implementing five stage pipeline, M.Randelzhofer
• Problem with Xilinx Impact under windowsXP, rakesh
  • <Possible follow-ups>
  • Problem with Xilinx Impact under windowsXP, rakesh
• CPLD design software under WINE?, Mika Leinonen
  • Re: CPLD design software under WINE?, troy . scott
  • <Possible follow-ups>
  • CPLD design software under WINE?, Mika Leinonen
    • Re: CPLD design software under WINE?, dlharmon
      • Re: CPLD design software under WINE?, Steven J. Hill
      • Re: CPLD design software under WINE?, Derek Gladding
    • Re: CPLD design software under WINE?, troy . scott
• xilinx fpga beginner question, Eric Yeh
  • Re: xilinx fpga beginner question, Peter Ryser
• Synplify Pro and automatic Retiming/Pipelining, Simon Heinzle
  • Re: Synplify Pro and automatic Retiming/Pipelining, Kolja Sulimma
  • Re: Synplify Pro and automatic Retiming/Pipelining, Ken McElvain
• Help me, zqhpnp@xxxxxxxxx
  • Re: Help me, Eli Hughes
    • Re: Help me, Kunal
• Ciappla, ciappalastringa
  • Re: Ciappla, ciappalastringa
• FPGA : PCI core needed, bijoy
  • Re: FPGA : PCI core needed, Antti Lukats
    • Re: FPGA : PCI core needed, bijoy
• Re: Any suggestions for prototyping in an ARM environment?, MikeD'
• Re: ISE 7.1i & Linux / reg code question, Eric Smith
• Linux and Platform USB Cable, Waage
  • Re: Linux and Platform USB Cable, Sylvain Munaut
    • Re: Linux and Platform USB Cable, Waage
      • Re: Linux and Platform USB Cable, Paul Hartke
• Xilinx ML403 Board Beginner, Brad Smallridge
  • Re: Xilinx ML403 Board Beginner, Peter Alfke
    • Re: Xilinx ML403 Board Beginner, Kunal
      • Re: Xilinx ML403 Board Beginner, Brad Smallridge
      • Re: Xilinx ML403 Board Beginner, Kunal
    • Re: Xilinx ML403 Board Beginner, onenanometer@xxxxxxxxx
• Anyone remember the really early Xilinx FPGAs?, Mike
  • Re: Anyone remember the really early Xilinx FPGAs?, Austin Lesea
  • Re: Anyone remember the really early Xilinx FPGAs?, Mike Treseler
  • Re: Anyone remember the really early Xilinx FPGAs?, Peter Alfke
    • Re: Anyone remember the really early Xilinx FPGAs?, Austin Lesea
  • Re: Anyone remember the really early Xilinx FPGAs?, Philip Freidin
    • Re: Anyone remember the really early Xilinx FPGAs?, tom
    • Re: Anyone remember the really early Xilinx FPGAs?, tom
      • Re: Anyone remember the really early Xilinx FPGAs?, tom
      • Re: Anyone remember the really early Xilinx FPGAs?, Peter Alfke
      • Re: Anyone remember the really early Xilinx FPGAs?, Symon
      • Re: Anyone remember the really early Xilinx FPGAs?, Peter Alfke
      • Re: Anyone remember the really early Xilinx FPGAs?, austin
      • Re: Anyone remember the really early Xilinx FPGAs?, GPE
      • Re: Anyone remember the really early Xilinx FPGAs?, Symon
      • Re: Anyone remember the really early Xilinx FPGAs?, Symon
  • Re: Anyone remember the really early Xilinx FPGAs?, John Adair
  • Re: Anyone remember the really early Xilinx FPGAs?, Jan Coombs
• Xilinx EDK : mb-gcc linker errors with C++ features, Guru
• Re: computer upgrade time., Ray Andraka
• Storing a file onto FPGA, Robert
  • Re: Storing a file onto FPGA, Stephen Craven
    • Re: Storing a file onto FPGA, Robert
      • Re: Storing a file onto FPGA, Ray Andraka
      • Re: Storing a file onto FPGA, Robert
      • Re: Storing a file onto FPGA, backhus
      • Re: Storing a file onto FPGA, Kolja Sulimma
      • Re: Storing a file onto FPGA, backhus
      • Re: Storing a file onto FPGA, Robert
      • Re: Storing a file onto FPGA, Robert
      • Re: Storing a file onto FPGA, Ray Andraka
      • Re: Storing a file onto FPGA, Philip Freidin
      • Re: Storing a file onto FPGA, Robert
      • Re: Storing a file onto FPGA, Symon
      • Message not available
      • Re: Storing a file onto FPGA, Symon
      • Re: Storing a file onto FPGA, Erik Widding
      • Re: Storing a file onto FPGA, Ray Andraka
      • Re: Storing a file onto FPGA, Symon
      • Re: Storing a file onto FPGA (the last word), John McCluskey
      • Re: Storing a file onto FPGA (the last word), backhus
      • Re: Storing a file onto FPGA (the last word), Ray Andraka
      • Re: Storing a file onto FPGA (the last word), John McCluskey
  • Re: Storing a file onto FPGA, cs_posting
• IO interface standard of fpga, zqhpnp@xxxxxxxxx
• Re: Data width change in opencores Ethernet MAC, Sylvain Munaut
• Simulink to hdl conversion, vssumesh
  • Re: Simulink to hdl conversion, kcl
  • Re: Simulink to hdl conversion, Ken McElvain
  • Re: Simulink to hdl conversion, Eric_at_AccelChip
• IOs on ML-310 Evaluation Board, Hendry
• RAMB16 primitive write/read collision differences betweem virtex2 and virtex4, Javier Castillo
  • Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4, John_H
    • Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4, Javier Castillo
  • Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4, Javier Castillo
    • Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4, Brian Davis
    • Message not available
      • Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4, Javier Castillo
  • Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4, Javier Castillo
• IDELAYCTRL floorplanner/fpga editor/pace problem, Tim Verstraete
  • Re: IDELAYCTRL floorplanner/fpga editor/pace problem, pipjockey
    • Re: IDELAYCTRL floorplanner/fpga editor/pace problem, Tim Verstraete
• NgdBuild:455, Ngd:Build:924 when using MGT XBERT, do_not_bend_42
• Re: Best FPGA for floating point performance, Ray Andraka
• User Library in ISE, xipn
• how to implement 8x8 circular shifter on FPGA, Enver
  • Re: how to implement 8x8 circular shifter on FPGA, Slurp
    • Re: how to implement 8x8 circular shifter on FPGA, Ray Andraka
  • Re: how to implement 8x8 circular shifter on FPGA, pipjockey
• Question regarding FPGA startup ROMs, Immo Birnbaum
  • Re: Question regarding FPGA startup ROMs, Jon Elson
  • Re: Question regarding FPGA startup ROMs, M.Randelzhofer
  • Re: Question regarding FPGA startup ROMs, Eli Hughes
  • Re: Question regarding FPGA startup ROMs, Thomas Womack
• stratix fpga pll, ebi
  • Re: stratix fpga pll, Rob
• How to Reduce Interconnects (VDD and VSS), fahadislam2002
  • Re: How to Reduce Interconnects (VDD and VSS), John_H
    • Re: How to Reduce Interconnects (VDD and VSS), Jeremy Stringer
      • Re: How to Reduce Interconnects (VDD and VSS), John_H
    • Re: How to Reduce Interconnects (VDD and VSS), jai.dhar@xxxxxxxxx
      • Re: How to Reduce Interconnects (VDD and VSS), John_H
      • Re: How to Reduce Interconnects (VDD and VSS), Hal Murray
      • Re: How to Reduce Interconnects (VDD and VSS), Jim Granville
      • Message not available
      • Re: How to Reduce Interconnects (VDD and VSS), Eric Smith
      • Message not available
      • Re: How to Reduce Interconnects (VDD and VSS), John_H
      • Re: How to Reduce Interconnects (VDD and VSS), PeteS
      • Re: How to Reduce Interconnects (VDD and VSS), jai.dhar@xxxxxxxxx
      • Re: How to Reduce Interconnects (VDD and VSS), PeteS
      • Re: How to Reduce Interconnects (VDD and VSS), jai.dhar@xxxxxxxxx
      • Re: How to Reduce Interconnects (VDD and VSS), jai.dhar@xxxxxxxxx
      • Re: How to Reduce Interconnects (VDD and VSS), PeteS
      • Re: How to Reduce Interconnects (VDD and VSS), jai.dhar@xxxxxxxxx
  • re:How to Reduce Interconnects (VDD and VSS), fahadislam2002
    • Re: How to Reduce Interconnects (VDD and VSS), Bevan Weiss
• question: timing constraint for clock enable, Stephan Flock
  • Re: question: timing constraint for clock enable, Newman
  • Re: question: timing constraint for clock enable, Symon
    • Re: question: timing constraint for clock enable, Stephan Flock
• LUT 4:1 VS FF, Claudio
  • Message not available
    • Re: LUT 4:1 VS FF, Claudio
      • Message not available
      • Re: LUT 4:1 VS FF, Claudio
      • Re: LUT 4:1 VS FF, Hal Murray
      • Re: LUT 4:1 VS FF, Claudio
      • Re: LUT 4:1 VS FF, Peter Alfke
• ModelSim XE: Can't import vital 2000 library, Jörg Rockstroh
  • Re: ModelSim XE: Can't import vital 2000 library, Jörg Rockstroh
• Problems with phase shift dcm, creemers_roger
• Re: Synchronizer Flip Flop / Metastability, Hal Murray
• converting 12v signal to 3.3v, kcl
  • Re: converting 12v signal to 3.3v, kcl
    • Re: converting 12v signal to 3.3v, Simon Peacock
      • Re: converting 12v signal to 3.3v, DerekSimmons@xxxxxxxxxxxxxxx
      • Re: converting 12v signal to 3.3v, Jon Elson
      • Message not available
      • Re: converting 12v signal to 3.3v, Symon
      • Message not available
      • Re: converting 12v signal to 3.3v, Symon
      • Re: converting 12v signal to 3.3v, Kolja Sulimma
      • [OT]Re: converting 12v signal to 3.3v, Symon
      • Re: [OT]Re: converting 12v signal to 3.3v, Mark McDougall
      • Re: [OT]Re: converting 12v signal to 3.3v, Hal Murray
      • Message not available
      • [Going OT] Automotive Re: converting 12v signal to 3.3v, Martin Thompson
      • Re: [Going OT] Automotive Re: converting 12v signal to 3.3v, Martin Thompson
    • Re: converting 12v signal to 3.3v, MM
• iVerilog / VVP output to GTKwave., Grahame Kelly
  • Re: iVerilog / VVP output to GTKwave., allanherriman
    • Re: iVerilog / VVP output to GTKwave., Grahame Kelly
  • Re: iVerilog / VVP output to GTKwave., Guenter
• Compiling Altera LPM FIFO into Modelsim Error, pinod01
  • Re: Compiling Altera LPM FIFO into Modelsim Error, Subroto Datta
    • Re: Compiling Altera LPM FIFO into Modelsim Error, pinod01
• 64 bit processor for FPGA workstation?, Ray Andraka
  • Re: 64 bit processor for FPGA workstation?, allanherriman
    • Re: 64 bit processor for FPGA workstation?, doomeddave
      • Re: 64 bit processor for FPGA workstation?, gallen
      • Re: 64 bit processor for FPGA workstation?, Ray Andraka
  • Re: 64 bit processor for FPGA workstation?, Phil Tomson
• What is a "full custom" design?, Paul Marciano
  • Re: What is a "full custom" design?, Stephen Craven
    • Re: What is a "full custom" design?, vssumesh
      • Re: What is a "full custom" design?, gallen
      • Re: What is a "full custom" design?, vssumesh
• Xilinx Chipscope VIO Core Utilization, happydude32905
  • Re: Xilinx Chipscope VIO Core Utilization, Ed McGettigan
  • Re: Xilinx Chipscope VIO Core Utilization, Antti Lukats
• Eliminates meta stability (yes or no)?, Bill
  • Re: Eliminates meta stability (yes or no)?, johnp
    • Re: Eliminates meta stability (yes or no)?, Bill
    • Re: Eliminates meta stability (yes or no)?, Bill
  • Re: Eliminates meta stability (yes or no)?, Phil Hays
    • Re: Eliminates meta stability (yes or no)?, Peter Alfke
  • Re: Eliminates meta stability (yes or no)?, rhnlogic@xxxxxxxxx
  • Re: Eliminates meta stability (yes or no)?, Hal Murray
• Verilog VPI, slawc
• Using the BSCAN primitives, Sylvain Munaut
  • Re: Using the BSCAN primitives, Sandro
    • Re: Using the BSCAN primitives, Sylvain Munaut
  • Re: Using the BSCAN primitives, derek
• Xilinx IPIF PLB Master Update, Eli Hughes
  • Re: Xilinx IPIF PLB Master Update, Sylvain Munaut
• How many decoupling capacitors need on one device?, river064
  • Re: How many decoupling capacitors need on one device?, Austin Lesea
  • Re: How many decoupling capacitors need on one device?, John Adair
  • Re: How many decoupling capacitors need on one device?, Gary Pace
  • Re: How many decoupling capacitors need on one device?, John Larkin
    • Re: How many decoupling capacitors need on one device?, PeteS
• Questions on DCI split termination of spartan-3, codejk
• Re: Power on reset generation in FPGA, Austin Lesea
  • Re: Power on reset generation in FPGA, Andrew FPGA
  • <Possible follow-ups>
  • Re: Power on reset generation in FPGA, Ray Andraka
• Clock routing, patrick . melet
  • Re: Clock routing, ALuPin
• systemc to verilog translator v0.5, Javier Castillo
• VHDL : Use concatenation on port mapping, Georgios Sidiropoulos
  • Re: VHDL : Use concatenation on port mapping, Georgios Sidiropoulos
    • Re: VHDL : Use concatenation on port mapping, ALuPin
    • Re: VHDL : Use concatenation on port mapping, Simon Peacock
  • Re: VHDL : Use concatenation on port mapping, Jim Lewis
    • Re: VHDL : Use concatenation on port mapping, Newman
• Yet another NGDBUILD 455 problem, merlin_jiang
• Re: fixed point dot product with log2(n) pipe stages in vhdl, Jonathan Bromley
• Re: 16-bit microprocessor dore for Actel, Jonathan Bromley
  • Re: 16-bit microprocessor dore for Actel, Antti Lukats
    • Re: 16-bit microprocessor dore for Actel, Jonathan Bromley
      • Re: 16-bit microprocessor dore for Actel, Antti Lukats
  • Re: 16-bit microprocessor dore for Actel, Jim Granville
• 16550 VHDL code, Jackolantern25
  • Re: 16550 VHDL code, Mark McDougall
• Library Simprim cannot be found?, seabrench
  • Re: Library Simprim cannot be found?, Aurelian Lazarut
    • Re: Library Simprim cannot be found?, seabrench
• 3rd party JTAG cables/controllers for Virtex-4, Waage
  • Re: 3rd party JTAG cables/controllers for Virtex-4, Simon Peacock
  • Re: 3rd party JTAG cables/controllers for Virtex-4, John Adair
    • Re: 3rd party JTAG cables/controllers for Virtex-4, Waage
      • Re: 3rd party JTAG cables/controllers for Virtex-4, Simon Peacock
• Opal help please, fpbankroll
• New Ethernet Development board, open-source, jai.dhar@xxxxxxxxx
• PowerPC interrupt latency, Eli Hughes
  • Re: PowerPC interrupt latency, Peter Ryser
• re:9bit vga with resistors., mice
  • <Possible follow-ups>
  • 9bit vga with resistors., mice
    • Re: 9bit vga with resistors., Robert Finch
• ISE 7.1i installing issues on Windows XP Pro Sp2., Brijesh
• Question about metastability that's been on my mind for a while, Michael Chan
  • Re: Question about metastability that's been on my mind for a while, Hubble
    • Re: Question about metastability that's been on my mind for a while, Michael Chan
      • Re: Question about metastability that's been on my mind for a while, Hubble
      • Re: Question about metastability that's been on my mind for a while, rhnlogic@xxxxxxxxx
  • Re: Question about metastability that's been on my mind for a while, Klaus Falser
  • Re: Question about metastability that's been on my mind for a while, Raymund Hofmann
    • Re: Question about metastability that's been on my mind for a while, Symon
      • Re: Question about metastability that's been on my mind for a while, rhnlogic@xxxxxxxxx
      • Re: Question about metastability that's been on my mind for a while, Symon
      • Re: Question about metastability that's been on my mind for a while, Raymund Hofmann
      • Re: Question about metastability that's been on my mind for a while, Bob Perlman
      • Re: Question about metastability that's been on my mind for a while, nospam
      • Re: Question about metastability that's been on my mind for a while, Raymund Hofmann
      • Re: Question about metastability that's been on my mind for a while, Bob Perlman
    • Re: Question about metastability that's been on my mind for a while - mine too, I lived it, Austin Lesea
      • Re: Question about metastability that's been on my mind for a while - mine too, I lived it, Peter Alfke
• Xilinx WebPack and command line, Remis Norvilis
  • Re: Xilinx WebPack and command line, devb
    • Re: Xilinx WebPack and command line, Sandro
      • Re: Xilinx WebPack and command line, Antti Lukats
      • Re: Xilinx WebPack and command line, devb
      • Re: Xilinx WebPack and command line, Sandro
  • Message not available
    • Re: Xilinx WebPack and command line, Remis Norvilis
  • Re: Xilinx WebPack and command line, Kevin Brace
• Virtex4 shift register layout: Horizontal or vertical?, jjohnson
  • Re: Virtex4 shift register layout: Horizontal or vertical?, Antti Lukats
  • Re: Virtex4 shift register layout: Horizontal or vertical?, Kolja Sulimma
  • Re: Virtex4 shift register layout: Horizontal or vertical?, Ray Andraka
• FPGA behaviour when its used resource is >90% ?, kkumar
  • Re: FPGA behaviour when its used resource is >90% ?, ALuPin
  • Re: FPGA behaviour when its used resource is >90% ?, Antti Lukats
    • Re: FPGA behaviour when its used resource is >90% ?, bijoy
      • Re: FPGA behaviour when its used resource is >90% ?, Simon Peacock
  • Re: FPGA behaviour when its used resource is >90% ?, Zara
  • Re: FPGA behaviour when its used resource is >90% ?, Aurelian Lazarut
    • Re: FPGA behaviour when its used resource is >90% ?, Mike Harrison
  • Re: FPGA behaviour when its used resource is >90% ?, Nial Stewart
• DDR constraints in Xilinx/UCF, Synplicity?, jjohnson
  • Re: DDR constraints in Xilinx/UCF, Synplicity?, Antti Lukats
    • Re: DDR constraints in Xilinx/UCF, Synplicity?, jjohnson
• Raggedstone1, John Adair
• matrix inversion in hardware, rafaelcns
  • Re: matrix inversion in hardware, jjohnson
• Xilinx PLB IPIF Master, Eli Hughes
  • Re: Xilinx PLB IPIF Master, alan
    • Re: Xilinx PLB IPIF Master, Eli Hughes
      • Re: Xilinx PLB IPIF Master, alan
• Verification using Chipscope, Anuja
  • Re: Verification using Chipscope, sovan
• Altera Gate Delay Simulation, kedarpapte
  • Re: Altera Gate Delay Simulation, Ben Twijnstra
  • Re: Altera Gate Delay Simulation, morpheus
    • Re: Altera Gate Delay Simulation, kedarpapte
    • Re: Altera Gate Delay Simulation, kedarpapte
      • Re: Altera Gate Delay Simulation, Albert Chang
• ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?, J buytaert
  • Re: ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?, Neill A
    • Message not available
      • Re: ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?, Neill A
  • Re: ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?, Antti Lukats
• FSM with High load on clock signal, Marco
  • Re: FSM with High load on clock signal, Jeremy Stringer
  • Re: FSM with High load on clock signal, Symon
    • Re: FSM with High load on clock signal, Marco
      • Re: FSM with High load on clock signal, Symon
      • Message not available
      • Message not available
      • Re: FSM with High load on clock signal, Marco
      • Re: FSM with High load on clock signal, Symon
      • Re: FSM with High load on clock signal, Marco
• Actel Libero upgrade - problem with clk pin - Synplify, Marie
  • Re: Actel Libero upgrade - problem with clk pin - Synplify, Neill A
    • Re: Actel Libero upgrade - problem with clk pin - Synplify, Marie
      • Re: Actel Libero upgrade - problem with clk pin - Synplify, Neill A
      • Re: Actel Libero upgrade - problem with clk pin - Synplify, Marie
• .lib file for Xilinx FPGAs?, Simon Heinzle
  • Re: .lib file for Xilinx FPGAs?, Simon Peacock
    • Re: .lib file for Xilinx FPGAs?, Simon Heinzle
      • Re: .lib file for Xilinx FPGAs?, Kolja Sulimma
  • Re: .lib file for Xilinx FPGAs?, Kolja Sulimma
  • Re: .lib file for Xilinx FPGAs?, Simon Heinzle
• Re: ise (lin64) and debian, Derek Gladding
  • <Possible follow-ups>
  • Re: ise (lin64) and debian, Adrian Knoth
• evaluation edk in Spartan-3 starter kit, aholtzma
  • Re: evaluation edk in Spartan-3 starter kit, Newman
    • Re: evaluation edk in Spartan-3 starter kit, aholtzma
      • Re: evaluation edk in Spartan-3 starter kit, Newman
      • Re: evaluation edk in Spartan-3 starter kit, news.hinet.net
      • Re: evaluation edk in Spartan-3 starter kit, Michael Schuster
      • Re: evaluation edk in Spartan-3 starter kit, aholtzma
      • Re: evaluation edk in Spartan-3 starter kit, Michael Schuster
      • Re: evaluation edk in Spartan-3 starter kit, aholtzma
      • Re: evaluation edk in Spartan-3 starter kit, Michael Schuster
      • Re: evaluation edk in Spartan-3 starter kit, aholtzma
  • Re: evaluation edk in Spartan-3 starter kit, Leon
    • Re: evaluation edk in Spartan-3 starter kit, aholtzma
• Xilinx ISE 7.1i file management, cyd
  • Re: Xilinx ISE 7.1i file management, Diego Lillo
• Re: Xilinx ISE 7.1i Portability Error, Matthew Plante
• re:Xilinx ISE WebPACK-7.1i on NetBSD, Darius
  • Re: re:Xilinx ISE WebPACK-7.1i on NetBSD, tlb
• Where to get informations about Virtex 4 FX Engineering Samples, Peter Rauschert
  • Re: Where to get informations about Virtex 4 FX Engineering Samples, Antti Lukats
    • Re: Where to get informations about Virtex 4 FX Engineering Samples, Peter Rauschert
      • Re: Where to get informations about Virtex 4 FX Engineering Samples, zeeman_be
      • Re: Where to get informations about Virtex 4 FX Engineering Samples, Simon Peacock
      • Re: Where to get informations about Virtex 4 FX Engineering Samples, Austin Lesea
• XMD and xilmfs help, Joseph
  • Re: XMD and xilmfs help, Joseph
• I'm desperate... EDK project simulation, Melissa Vetromille
  • Re: I'm desperate... EDK project simulation, Zara
  • Re: I'm desperate... EDK project simulation, Sylvain Munaut
  • Re: I'm desperate... EDK project simulation, Melissa Vetromille
  • Re: I'm desperate... EDK project simulation, Melissa Vetromille
    • Re: I'm desperate... EDK project simulation, Zara
  • Re: I'm desperate... EDK project simulation, Melissa Vetromille
    • Re: I'm desperate... EDK project simulation, Zara
• Systolic array architectures, timotoole
  • Re: Systolic array architectures, Kolja Sulimma
    • Re: Systolic array architectures, timotoole
      • Re: Systolic array architectures, Kolja Sulimma
• How to make XST understand to pack mux(A,B,A+B) in a single level ?, Sylvain Munaut
  • Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?, John_H
    • Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?, Sylvain Munaut
      • Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?, quark01
      • Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?, John_H
      • Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?, Sylvain Munaut
      • Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?, John_H
      • Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?, Sylvain Munaut
  • Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?, Kolja Sulimma
• Radiation + CoolRunner2 CPLD?, Bob
  • Re: Radiation + CoolRunner2 CPLD?, Austin Lesea
    • Re: Radiation + CoolRunner2 CPLD?, Bob
      • Re: Radiation + CoolRunner2 CPLD?, Austin Lesea
• Xilinx IMPACT Problem... detects 101 unknown devices, Subhasri krishnan
  • Re: Xilinx IMPACT Problem... detects 101 unknown devices, Andy Peters
    • Re: Xilinx IMPACT Problem... detects 101 unknown devices, Subhasri krishnan
      • Re: Xilinx IMPACT Problem... detects 101 unknown devices, Ed McGettigan
      • Re: Xilinx IMPACT Problem... detects 101 unknown devices, Sean Durkin
      • Re: Xilinx IMPACT Problem... detects 101 unknown devices, Jeremy Stringer
  • Re: Xilinx IMPACT Problem... detects 101 unknown devices, Brad Smallridge
  • Re: Xilinx IMPACT Problem... detects 101 unknown devices, Klaus Bickertt
    • Re: Xilinx IMPACT Problem... detects 101 unknown devices, Simon Peacock
      • Re: Xilinx IMPACT Problem... detects 101 unknown devices, Subhasri krishnan
      • Re: Xilinx IMPACT Problem... detects 101 unknown devices, Newman
      • Re: Xilinx IMPACT Problem... detects 101 unknown devices, Klaus Bickert
• Altera NIOS PIO interrupt problem, Monica
  • Re: Altera NIOS PIO interrupt problem, GMM50
• High Load, Marco
  • Re: High Load, Antti Lukats
    • Re: High Load, Marco
    • Re: High Load, Marco
      • Re: High Load, Simon Peacock
      • Re: High Load, Marco
      • Re: High Load, Simon Peacock
      • Re: High Load, Marco
      • Re: High Load, Marco
• Floating point multiplication on Spartan3 device, codejk
  • Re: Floating point multiplication on Spartan3 device, Stephen Craven
    • Re: Floating point multiplication on Spartan3 device, codejk
      • Re: Floating point multiplication on Spartan3 device, Robin Bruce
      • Re: Floating point multiplication on Spartan3 device, codejk
  • Re: Floating point multiplication on Spartan3 device, Ben Jones
    • Re: Floating point multiplication on Spartan3 device, codejk
• Avoiding meta stability?, Bill
  • Re: Avoiding meta stability?, rhnlogic@xxxxxxxxx
    • Re: Avoiding meta stability?, Peter Alfke
      • Re: Avoiding meta stability?, rhnlogic@xxxxxxxxx
      • Re: Avoiding meta stability?, Bob Perlman
      • Re: Avoiding meta stability?, Peter Alfke
      • Re: Avoiding meta stability?, Simon Peacock
      • Re: Avoiding meta stability?, Paul Marciano
      • Re: Avoiding meta stability?, Austin Lesea
      • Re: Avoiding meta stability? No where in this thread..., austin
      • Re: Avoiding meta stability? No where in this thread..., Philip Freidin
      • Re: Avoiding meta stability? No where in this thread..., Phil Hays
      • Re: Avoiding meta stability? No where in this thread..., Paul Marciano
      • Avoiding meta stability? Finally...? Don't use SRL16 as a synchronizer, Austin Lesea
      • Re: Avoiding meta stability? Finally...? Don't use SRL16 as a synchronizer, Brian Philofsky
      • RLOC Map error! Help!, Paul Marciano
      • Re: Avoiding meta stability? No where in this thread..., Austin Lesea
      • Re: Avoiding meta stability? No where in this thread..., Philip Freidin
      • Re: Avoiding meta stability?, Phil Hays
      • Re: Avoiding meta stability?, Paul Marciano
      • Re: Avoiding meta stability?, Simon Peacock
      • Re: Avoiding meta stability?, Ricardo
      • Re: Avoiding meta stability?, Peter Alfke
      • Re: Avoiding meta stability?, Simon Peacock
      • Re: Avoiding meta stability?, Bill
      • Re: Avoiding meta stability?, Bob Perlman
      • Re: Avoiding meta stability?, Bill
      • Re: Avoiding meta stability?, Bill
      • Re: Avoiding meta stability?, Symon
      • Re: Avoiding meta stability?, Bill
      • Re: Avoiding meta stability?, Peter Alfke
      • Re: Avoiding meta stability?, rhnlogic@xxxxxxxxx
      • Re: Avoiding meta stability?, Phil Hays
      • Re: Avoiding meta stability?, Phil Hays
      • Re: Avoiding meta stability?, Ray Andraka
      • Re: Avoiding meta stability?, Peter Alfke
      • Re: Avoiding meta stability?, rhnlogic@xxxxxxxxx
  • Re: Avoiding meta stability?, Philip Freidin
    • Re: Avoiding meta stability?, Peter Alfke
      • Re: Avoiding meta stability?, Ray Andraka
      • Re: Avoiding meta stability?, Peter Alfke
    • Re: Avoiding meta stability?, austin
      • Re: Avoiding meta stability?, Simon Peacock
  • Re: Avoiding meta stability?, nospam.eric@xxxxxxxxx
    • Re: Avoiding meta stability?, Symon
• Problems in simulating EDK system, mvetromille
• re:FPGA : Decimation Filter, seb_tech_fr
• vhdl question, CMOS
  • Re: vhdl question, Mike Treseler
    • Re: vhdl question, CMOS
    • Re: vhdl question, Simon Peacock
  • Re: vhdl question, nospam.eric@xxxxxxxxx
  • Re: vhdl question, Brad Smallridge
  • Re: vhdl question, Andy Peters
    • Re: vhdl question, CMOS
      • Re: vhdl question, Nicolas Matringe
      • Re: vhdl question, Simon Peacock
      • Re: vhdl question, CMOS
      • Re: vhdl question, Mike Treseler
      • Re: vhdl question, Andy Peters
• going backwards, Xilinx ISE 7.1 to ISE 6.3, Rob Young
  • Re: going backwards, Xilinx ISE 7.1 to ISE 6.3, Phil Hays
• Re: Antti is back, Sandro
• Weird problem in Xilinx WebPack ISE PACE 7.1SP4, fpgagrp
• RLDRAM-II controller - Read problem, Elling Diesen
• Re: Altera why so QUIET !?, Ben Twijnstra
  • Re: Altera why so QUIET !?, austin
    • Re: Altera why so QUIET !?, Ben Twijnstra
      • EasyPath, demystified, Austin Lesea
      • Re: EasyPath, demystified, Adam Megacz
      • Re: EasyPath, demystified, Austin Lesea
      • Re: EasyPath, demystified, Ben Twijnstra
      • Re: EasyPath, demystified, Austin Lesea
      • Re: EasyPath, demystified, johnp
      • Re: EasyPath, demystified, Adam Megacz
      • Re: EasyPath, demystified, Ray Andraka
      • Re: EasyPath, demystified, Ben Twijnstra
      • Re: EasyPath, demystified, Ben Jones
      • Re: EasyPath, demystified, Ben Twijnstra
      • Re: EasyPath, demystified, Austin Lesea
      • Re: EasyPath, demystified, Ben Twijnstra
• Re: Using LogicCORE on development board with Web ISE, Kevin Brace
  • Re: Using LogicCORE on development board with Web ISE, G.H. Hardy
    • Re: Using LogicCORE on development board with Web ISE, Kevin Brace
• Xilinx/Linux: sch2vhdl not working very hard, Paul Boven
  • Re: Xilinx/Linux: sch2vhdl not working very hard, Georg Acher
    • Re: Xilinx/Linux: sch2vhdl not working very hard, Paul Boven
• Re: altera new bee, altera_smells
  • Re: altera new bee, Philip Freidin
    • Re: altera new bee, Simon Peacock
• Re: Prob in Synthesizing and Simulating large Mux, Ray Andraka
  • Re: Prob in Synthesizing and Simulating large Mux, vssumesh
    • Re: Prob in Synthesizing and Simulating large Mux, Simon Peacock
      • Re: Prob in Synthesizing and Simulating large Mux, vssumesh
      • Message not available
      • Re: Prob in Synthesizing and Simulating large Mux, vssumesh
      • Re: Prob in Synthesizing and Simulating large Mux, Simon Peacock
      • Re: Prob in Synthesizing and Simulating large Mux, vssumesh
      • Re: Prob in Synthesizing and Simulating large Mux, Andy Peters
      • Re: Prob in Synthesizing and Simulating large Mux, Simon Peacock
      • Re: Prob in Synthesizing and Simulating large Mux, vssumesh
      • Re: Prob in Synthesizing and Simulating large Mux, Simon Peacock
• Re: I, Wish: I had an Spartan-3e NOW!, seannstifler69
  • Re: I, Wish: I had an Spartan-3e NOW!, Newman
  • Re: I, Wish: I had an Spartan-3e NOW!, Peter Alfke
• Re: Req to Xilinx: eCos port for Microblaze, Ram
• for...generate loop with generics, constants (vhdl), geoffrey wall
  • Re: for...generate loop with generics, constants (vhdl), Nitesh
    • Re: for...generate loop with generics, constants (vhdl), radarman
• Inferring design elements in ISE tool, sk.sulabh@xxxxxxxxx
  • Re: Inferring design elements in ISE tool, Andy Peters
    • Re: Inferring design elements in ISE tool, sk.sulabh@xxxxxxxxx
• Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz, wanch
  • <Possible follow-ups>
  • Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz, wanch
    • Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz, Antti Lukats
  • Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz, Brian Davis
• Re: Count "1" bit in bit stream, Thomas Rudloff
• Re: Xilinx dev board with high quality video?, Antti Lukats
  • Re: Xilinx dev board with high quality video?, Pete Fraser
  • Re: Xilinx dev board with high quality video?, Simon Peacock
    • Re: Xilinx dev board with high quality video?, Antti Lukats
      • Re: Xilinx dev board with high quality video?, Simon Peacock
  • Message not available
    • Re: Xilinx dev board with high quality video?, Antti Lukats
  • <Possible follow-ups>
  • Re: Xilinx dev board with high quality video?, Brad Smallridge
    • Re: Xilinx dev board with high quality video?, Pete Fraser
      • Re: Xilinx dev board with high quality video?, Thomas Entner
      • Message not available
      • Re: Xilinx dev board with high quality video?, Jecel
      • Re: Xilinx dev board with high quality video?, Ed McGettigan
      • Re: Xilinx dev board with high quality video?, Jecel
      • Re: Xilinx dev board with high quality video?, Pete Fraser
      • Re: Xilinx dev board with high quality video?, Antonio Pasini
      • Re: Xilinx dev board with high quality video?, Jecel
      • Message not available
      • Re: Xilinx dev board with high quality video?, Antti Lukats
      • Re: Xilinx dev board with high quality video?, Ed McGettigan
      • Re: Xilinx dev board with high quality video?, Antti Lukats
      • Re: Xilinx dev board with high quality video?, Simon Peacock
• Re: Prevue - FPGA Dev Board Sale, John Adair
  • <Possible follow-ups>
  • Re: Prevue - FPGA Dev Board Sale, Heinz-Jürgen Oertel
    • Re: Prevue - FPGA Dev Board Sale, John Adair
  • Re: Prevue - FPGA Dev Board Sale, Kevin Brace
• VHDL 2 dimension array, eeh
  • Re: VHDL 2 dimension array, Simon Peacock
    • Re: VHDL 2 dimension array, Karthikeyan Subramaniyam
      • Re: VHDL 2 dimension array, Simon Peacock
    • Re: VHDL 2 dimension array, eeh
• re:Testbench using Modelsim/VHDL - simple signal generation pro, perica
• Synthesis with Icarus Verilog, Waage
• Re: Xilinx and Lattice tools on one machine?, Gabor
• More than one embedded system in ISE, Francis St-Pierre
  • Re: More than one embedded system in ISE, Zara
    • Re: More than one embedded system in ISE, Francis
      • Re: More than one embedded system in ISE, Zara
• ISE does not initialize the bitstream of a EDK project, Francis
  • Re: ISE does not initialize the bitstream of a EDK project, Antti Lukats
  • Re: ISE does not initialize the bitstream of a EDK project, Zara
  • <Possible follow-ups>
  • ISE does not initialize the bitstream of a EDK project, Francis St-Pierre
    • Re: ISE does not initialize the bitstream of a EDK project, Newman
      • Re: ISE does not initialize the bitstream of a EDK project, Francis
• Re: PCB Software...., henrique . portela
  • Re: PCB Software...., icegray
  • <Possible follow-ups>
  • Re: PCB Software...., Simon Peacock
• Virtex-4 FX20 PPC405 Startup Issue, Chris
  • Re: Virtex-4 FX20 PPC405 Startup Issue, Florian
  • Re: Virtex-4 FX20 PPC405 Startup Issue, wiggs
  • Re: Virtex-4 FX20 PPC405 Startup Issue, Jim Granville
    • Re: Virtex-4 FX20 PPC405 Startup Issue, wiggs
  • Re: Virtex-4 FX20 PPC405 Startup Issue, rwightman
    • Re: Virtex-4 FX20 PPC405 Startup Issue, Chris
  • Re: Virtex-4 FX20 PPC405 Startup Issue, Peter Ryser
    • Re: Virtex-4 FX20 PPC405 Startup Issue, Peter Ryser
• reading bits using JBits 3.0, sarnaths@xxxxxxxxx

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newsgroups.derkeiler.com  > Archive  > Comp  > comp.arch.fpga  > 2005-10