RE: vhdl state maching problem

I would second that ... Sorry about doing your homework....

1/ Synchronous counter desperately needs a clock.. you will get funny in
between states when multiple bits transition simultaneously. And the state
machine will quickly be in left field.

2/ Simulators need a reset.

3/ You need to assign state.. or better still, ignore next_state and just
use state.

4/ Be nice to people who follow and give processes sensible names and add
comments... no comments, no marks in my book

5/ what happens to ram_counter_w when it hits 131071 and wants to increment?


library ieee;
use ieee.std_logic_unsigned.all;

type state_type is (
rw_1, rw_2, rw_3
);
signal state: state_type;

signal ram_counter_w: integer range 0 to 131071;

state_machine : process (clk) is
begin
-- add an async reset ?? or a synchronized reset

if rising_edge(clk) then

if ((reset = '1') or (start = '0')) then
state <= rw_1;
ram_counter_w <= 0;
else
case state is
when rw_1 =>
state <= rw_2;
ram_counter_w <= ram_counter_w + 1;

when rw_2 =>
if (ram_counter_w = 131070) then
state <= rw_3;
else
state <= rw_1;
end if;

when rw_3 =>
-- some statements...

when others => -- Default case if reset or some crap happens!
-- some statements

end case;
end if;
end process state_machine;



"Nicolas Matringe" <nic_o_mat@xxxxxxx> wrote in message
news:1127803075.305910.74310@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
> Hello 'CMOS'
> It is usually a very bad idea to use a signal in the combinational
> process that updates it because it describes an asynchronous loop.
> I think you should use a synchronous process instead.
>
> Nicolas
>


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