Re: Xilinx ModelSim VHDL Running Two Models
- From: "Brad Smallridge" <bradsmallridge@xxxxxxxxxxxxxx>
- Date: Thu, 22 Sep 2005 08:21:59 -0700
Well, maybe you can show me an example, because I simply
don't get it. You say you instantiate the CPU, memory, etc,
but how does the simulator know what is connected to what?
Perhaps you can snip out one of your test-benches designs with
bidirectional signals for me and the group?
"Nicolas Matringe" <nic_o_mat@xxxxxxx> wrote in message
news:1127371032.791876.191140@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
> Brad
> I think you need a tutorial on testbenches...
> The usual way is to create a design (let's call it 'design') that will
> be synthesized. Then you create some sort of wrapper, the testbench,
> usually called design_tb in which you instantiate your design and all
> its environment (CPU, memory, DAC, ADC... ). This is where you will
> also generate the clock and reset signals.
> Don't worry about bidirectionnal signals at the testbench level. Treat
> all signals the same.
>
> Nicolas
>
.
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