comp.arch.fpga

• Date Index

• fixed point dot product with log2(n) pipe stages in vhdl, geoffrey wall
• Xilinx ISE 7.1i Portability Error, Matthew Plante
• Xilinx dev board with high quality video?, Pete Fraser
• PCB Software...., henrique . portela
  • Re: PCB Software...., Rene Tschaggelar
    • Re: PCB Software...., Falk Brunner
      • Re: PCB Software...., henrique . portela
      • Re: PCB Software...., Falk Brunner
• I, Wish: I had an Spartan-3e NOW!, Antti Lukats
• Lattice XP availability, Maki
  • Re: Lattice XP availability, Antti Lukats
    • Re: Lattice XP availability, Maki
      • Re: Lattice XP availability, Antti Lukats
• Prevue - FPGA Dev Board Sale, John Adair
  • Re: Prevue - FPGA Dev Board Sale, JASH
• Power on reset generation in FPGA, praveen . kantharajapura
  • Re: Power on reset generation in FPGA, Antti Lukats
  • Re: Power on reset generation in FPGA, Duane Clark
• Spartan II, Platfrom Flash, ISE 7.1 - SERIOUS PROBLEM, Antti Lukats
• looking for 1 beta-tester for PLD2HDL (XPLA3 edition) tool, Antti Lukats
• Prob in Synthesizing and Simulating large Mux, vssumesh
  • Re: Prob in Synthesizing and Simulating large Mux, Antti Lukats
    • Re: Prob in Synthesizing and Simulating large Mux, vssumesh
      • Re: Prob in Synthesizing and Simulating large Mux, Antti Lukats
      • Re: Prob in Synthesizing and Simulating large Mux, Kolja Sulimma
• Help! I lost my life (Again)!, Antti Lukats
• Altera why so QUIET !?, Antti Lukats
• best SPI flash configuration solution for Xilinx FPGA's, Antti Lukats
  • Re: best SPI flash configuration solution for Xilinx FPGA's, francesco_poderico
• very urgent, peri
  • Antti is back, Antti Lukats
    • Re: Antti is back, Jim Granville
    • Re: Antti is back, Thomas Entner
  • Re: very urgent, Antti Lukats
• High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz, wanch
  • Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz, Zara
  • Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz, Antti Lukats
• There is a way to instantiate 'N' VHDL components using a repetitive strutucture ?, ivan
  • Re: There is a way to instantiate 'N' VHDL components using a repetitive strutucture ?, Mark McDougall
  • Re: There is a way to instantiate 'N' VHDL components using a repetitive strutucture ?, backhus
    • Re: There is a way to instantiate 'N' VHDL components using a repetitive strutucture ?, Simon Peacock
• Re: 16-bit microprocessor dore for Actel, Hans
  • Re: 16-bit microprocessor dore for Actel, Antti Lukats
    • Re: 16-bit microprocessor dore for Actel, Hans
      • Re: 16-bit microprocessor dore for Actel, Antti Lukats
• Preloading SDRAM?, Subhasri krishnan
  • Re: Preloading SDRAM?, Gabor
    • Re: Preloading SDRAM?, Subhasri krishnan
      • Re: Preloading SDRAM?, Stephen Craven
      • Re: Preloading SDRAM?, Mike Harrison
  • Re: Preloading SDRAM?, Antti Lukats
  • Re: Preloading SDRAM?, Adrian Knoth
• CPLD program editing, abhi
  • Re: CPLD program editing, Rene Tschaggelar
  • Re: CPLD program editing, Antti Lukats
• Altera SOPC testbenching in Modelsim?, pinod01
• Synchronous & Asymchrnous Flip Flop Implementation, Andrew Greensted
  • Re: Synchronous & Asymchrnous Flip Flop Implementation, sulimma
    • Re: Synchronous & Asymchrnous Flip Flop Implementation, Andrew Greensted
  • Re: Synchronous & Asymchrnous Flip Flop Implementation, Mike Treseler
• ... failed to route using a CLK template, nospam.eric@xxxxxxxxx
  • Re: ... failed to route using a CLK template, Martin Thompson
• Re: Electronic Component Spare Parts ...., Jan Panteltje
• Using LogicCORE on development board with Web ISE, G.H. Hardy
  • Re: Using LogicCORE on development board with Web ISE, Antti Lukats
• Turion 64 performance, Marco
• newbie questions: Xilinx vs. Altera tools and parts, Kyle
  • Re: newbie questions: Xilinx vs. Altera tools and parts, Phil Hays
• re:generate systemACE file, rsotam
• Req to Xilinx: eCos port for Microblaze, Ram
  • Re: Req to Xilinx: eCos port for Microblaze, Peter Ryser
• Pricing for V2-Pro / V4-FX ?, Ram
• Using 3rd Party FPGA flows and Xilinx, Waage
• FPGA : Decimation Filter, bijoy
  • re:FPGA : Decimation Filter, seb_tech_fr
    • Re: FPGA : Decimation Filter, bijoy
• Re: IPIF interface not fast enough, Sean Durkin
  • Re: IPIF interface not fast enough, Frank van Eijkelenburg
  • <Possible follow-ups>
  • Re: IPIF interface not fast enough, Joseph Samson
• Internal clock for apex20ke, Designfreek
• Small C Compiler for Picoblaze, francesco_poderico
  • Re: Small C Compiler for Picoblaze, Jim Granville
  • Re: Small C Compiler for Picoblaze, Brad Smallridge
    • Re: Small C Compiler for Picoblaze, francesco_poderico
• a ISE installation problem on linux, springzzz@xxxxxxxxx
  • Re: a ISE installation problem on linux, Ram
    • Re: a ISE installation problem on linux, springzzz@xxxxxxxxx
• Dolby Digital AC-3 Decode on an FPGA - Possible ? Big ?, PeterC
  • Re: Dolby Digital AC-3 Decode on an FPGA - Possible ? Big ?, Kolja Sulimma
    • Re: Dolby Digital AC-3 Decode on an FPGA - Possible ? Big ?, aholtzma
• I am planning to purchase a Virtex-4 Eval board., Waage
  • Re: I am planning to purchase a Virtex-4 Eval board., Antti Lukats
  • Re: I am planning to purchase a Virtex-4 Eval board., JASH
  • Re: I am planning to purchase a Virtex-4 Eval board., JASH
• Sythesis software for Virtex-4, Waage
  • Re: Sythesis software for Virtex-4, Newman
  • Re: Sythesis software for Virtex-4, Newman
  • Re: Sythesis software for Virtex-4, Phil Hays
    • Message not available
      • Re: Sythesis software for Virtex-4, Ashok
      • Re: Sythesis software for Virtex-4, Waage
    • Message not available
      • Message not available
      • Re: Sythesis software for Virtex-4, John_H
• Spartan-3 starter kit and digilent jtag-usb cable, mice
  • re:Spartan-3 starter kit and digilent jtag-usb cable, mice
• Image Processing Algorithm based on FPGA?, seabrench
• Any suggestions for prototyping in an ARM environment?, MikeD'
  • Re: Any suggestions for prototyping in an ARM environment?, Kris Vorwerk
• How to run ngcbuild in windows xp environment?, Jason Hu
  • Re: How to run ngcbuild in windows xp environment?, Jason Hu
  • Re: How to run ngcbuild in windows xp environment?, Marco
• chipscope pro, Nitesh
  • Re: chipscope pro, Pasacco
    • Re: chipscope pro, Nitesh
      • Re: chipscope pro, Ed McGettigan
  • re:chipscope pro, seb_tech_fr
    • Re: chipscope pro, Nitesh
      • Re: chipscope pro, melbadri
      • Re: chipscope pro, Nitesh
  • Re: chipscope pro, Andy Peters
    • Re: chipscope pro, Nitesh
• Spartan3E - problem in creating LVDS DDR pads, assaf_sarfati
  • Re: Spartan3E - problem in creating LVDS DDR pads, austin
    • Re: Spartan3E - problem in creating LVDS DDR pads, Simon Peacock
    • Re: Spartan3E - problem in creating LVDS DDR pads, assaf_sarfati
• vhdl state maching problem, CMOS
  • Re: vhdl state maching problem, pinod01
  • Re: vhdl state maching problem, Brad Smallridge
  • Re: vhdl state maching problem, Nicolas Matringe
    • RE: vhdl state maching problem, Simon Peacock
      • Re: vhdl state maching problem, CMOS
  • Re: vhdl state maching problem, abeaujean@xxxxxxxxxxxxx
• Xilinx XUP + Linux (firmware loading problem!), S.T.
• ALTERA quartus II 5.0sp1 web edition can't program MAXII: error code 84, VAX9000
  • Re: ALTERA quartus II 5.0sp1 web edition can't program MAXII: error code 84, Subroto Datta
    • Re: ALTERA quartus II 5.0sp1 web edition can't program MAXII: error code 84, VAX9000
• Re: C-to-gates experiences, fortiz80@xxxxxxxxx
• Re: "Free" core and license, Guenter
  • Re: "Free" core and license, Marco
  • <Possible follow-ups>
  • Re: "Free" core and license, Rudolf Usselmann
• Re: Linux USB XUP board, S.T.
• External dpram similar to blockram of Xilinx device, codejk
  • Re: External dpram similar to blockram of Xilinx device, Mike Treseler
• lwip sockets on spartan 3 microblaze? Any examples?, K d
  • Re: lwip sockets on spartan 3 microblaze? Any examples?, francesco_poderico
    • Re: lwip sockets on spartan 3 microblaze? Any examples?, john . orlando
• altera new bee, zoharl3
  • Re: altera new bee, jai.dhar@xxxxxxxxx
• Altera_VHDL_support library into Modelsim?, pinod01
  • Re: Altera_VHDL_support library into Modelsim?, pinod01
    • Re: Altera_VHDL_support library into Modelsim?, pinod01
• question about creating RPM, shihhsin . hu
  • Re: question about creating RPM, Jason Hu
• Cyclone on a shared configuration bus, Piotr Wyderski
• re:Xilinx ISE WebPACK-7.1i on NetBSD, Darius
• jbits, GaLaKtIkUs?
  • Re: jbits, Adam Megacz
    • Re: jbits & reverse engineering, Austin Lesea
      • Re: jbits & reverse engineering, Adam Megacz
      • Re: jbits & reverse engineering, Austin Lesea
      • Re: jbits & reverse engineering, Simon Peacock
  • Re: jbits, GaLaKtIkUs?
  • Re: jbits, GaLaKtIkUs?
• Question on Metastability, GPE
  • Re: Question on Metastability, Peter Alfke
    • Re: Question on Metastability, GPE
      • Re: Question on Metastability, Jim Granville
    • Re: Question on Metastability, GPE
  • Re: Question on Metastability, Stephan Flock
    • Re: Question on Metastability, Peter Alfke
    • Re: Question on Metastability, GPE
      • Re: Question on Metastability, Gabor
      • Re: Question on Metastability, Jim Granville
      • Re: Question on Metastability, Peter Alfke
      • Re: Question on Metastability, Jim Granville
• 10G serial port with no FEC?, francisontheweb
  • Re: 10G serial port with no FEC?, Marc Randolph
• I need an Altera Excalib EPXA10 DDR Dev Board...anybody got one?, MikeD'
• 802.11g solution usable for FPGA design, Alexey Kulentsov
• ML403 dcm phase shift reference design... anyone has a copy ?, Antonio Pasini
• Power Management for Xilinx and Altera FPGAs, shorty
  • Re: Power Management for Xilinx and Altera FPGAs, Teo
• Synchronizer Flip Flop / Metastability, Simon Heinzle
  • Re: Synchronizer Flip Flop / Metastability, B. Joshua Rosen
  • Re: Synchronizer Flip Flop / Metastability, Gabor
  • Re: Synchronizer Flip Flop / Metastability, Phil Hays
  • Re: Synchronizer Flip Flop / Metastability, Symon
    • Re: Synchronizer Flip Flop / Metastability, Peter Alfke
      • Re: Synchronizer Flip Flop / Metastability, rhnlogic@xxxxxxxxx
      • Re: Synchronizer Flip Flop / Metastability, Peter Alfke
      • Re: Synchronizer Flip Flop / Metastability, Symon
      • Re: Synchronizer Flip Flop / Metastability, B. Joshua Rosen
      • Re: Synchronizer Flip Flop / Metastability, Symon
      • Re: Synchronizer Flip Flop / Metastability, rhnlogic@xxxxxxxxx
      • Re: Synchronizer Flip Flop / Metastability, Peter Alfke
  • Re: Synchronizer Flip Flop / Metastability, Simon Heinzle
• Need help in Flash simulation module., jerryjsy
  • <Possible follow-ups>
  • Need help in Flash simulation module., jerryjsy
• Announcement Free Symposium on the Future of Configurable Hardware, Mark Christiaens
• downlaoding bit files to Xilinx FPGA, Anuja
  • Re: downlaoding bit files to Xilinx FPGA, Falk Brunner
    • Re: downlaoding bit files to Xilinx FPGA, Anuja
      • Re: downlaoding bit files to Xilinx FPGA, johnp
      • Re: downlaoding bit files to Xilinx FPGA, johnp
      • Re: downlaoding bit files to Xilinx FPGA, Anuja
      • Re: downlaoding bit files to Xilinx FPGA, Falk Brunner
      • Re: downlaoding bit files to Xilinx FPGA, Anuja
  • Re: downlaoding bit files to Xilinx FPGA, Stephen Craven
    • Re: downlaoding bit files to Xilinx FPGA, Anuja
      • Re: downlaoding bit files to Xilinx FPGA, Philip Freidin
      • Re: downlaoding bit files to Xilinx FPGA, Anuja
      • Re: downlaoding bit files to Xilinx FPGA, Stephen Craven
• Hints for efficient 32 bit multiplier, Giox
  • Re: Hints for efficient 32 bit multiplier, mk
    • Re: Hints for efficient 32 bit multiplier, Sylvain Munaut
  • Re: Hints for efficient 32 bit multiplier, Ray Andraka
    • Re: Hints for efficient 32 bit multiplier, Giox
• Xilinx PAR -- WARNING:Route - CLK Net may have excessive skew..., Julian Kain
  • Re: Xilinx PAR -- WARNING:Route - CLK Net may have excessive skew..., Gabor
• USB communication using PCI Logicore, VB
• re:Modelsim XE, what's the latest version?, gliss
• opb ip master/slave...arbiter problems, melbadri
  • Re: opb ip master/slave...arbiter problems, Mohammed Elbadri
• Altera Programming Cables and EPCS16/64, CloneNumber66
• JBits query, sarnaths@xxxxxxxxx
  • Re: JBits query, Stephen Craven
• Xilinx Webpack Schematic, stbcasa
  • Re: Xilinx Webpack Schematic, Jon Elson
    • Re: Xilinx Webpack Schematic, Gabor
• data logging via JTAG?, janbeck
  • Re: data logging via JTAG?, Hans
• Re: Xilinx Spartan-3, acetylcholinerd@xxxxxxxxx
  • Message not available
    • Re: Xilinx Spartan-3, acetylcholinerd@xxxxxxxxx
      • Re: Xilinx Spartan-3, Austin Lesea
      • Re: Xilinx Spartan-3, sulimma
      • Re: Xilinx Spartan-3, acetylcholinerd@xxxxxxxxx
      • Re: Xilinx Spartan-3, Brian Davis
      • Re: Xilinx Spartan-3, Alvin Andries
      • Re: Xilinx Spartan-3, Brian Davis
• Xilinx ModelSim VHDL Running Two Models, Brad Smallridge
  • Re: Xilinx ModelSim VHDL Running Two Models, Andy Peters
    • Re: Xilinx ModelSim VHDL Running Two Models, Brad Smallridge
      • Re: Xilinx ModelSim VHDL Running Two Models, Nicolas Matringe
      • Re: Xilinx ModelSim VHDL Running Two Models, Nicolas Matringe
      • Re: Xilinx ModelSim VHDL Running Two Models, Brad Smallridge
      • Re: Xilinx ModelSim VHDL Running Two Models, Brad Smallridge
      • Re: Xilinx ModelSim VHDL Running Two Models, Andy Peters
      • Re: Xilinx ModelSim VHDL Running Two Models, Brad Smallridge
• Cyclone and NIOS II, GMM50
• Output register instantiation in Quartus, ALuPin
  • Re: Output register instantiation in Quartus, Subroto Datta
    • Re: Output register instantiation in Quartus, ALuPin
      • Re: Output register instantiation in Quartus, Subroto Datta
      • Re: Output register instantiation in Quartus, ALuPin
      • Re: Output register instantiation in Quartus, ALuPin
      • Re: Output register instantiation in Quartus, Vaughn Betz
      • Re: Output register instantiation in Quartus, ALuPin
      • Re: Output register instantiation in Quartus, Subroto Datta
• Count "1" bit in bit stream, hetfield
  • Re: Count "1" bit in bit stream, David Brown
    • Re: Count "1" bit in bit stream, hetfield
      • Re: Count "1" bit in bit stream, Thomas Womack
      • Re: Count "1" bit in bit stream, Peter Alfke
      • Re: Count "1" bit in bit stream, hetfield
• digilent USB2 module, CMOS
  • Re: digilent USB2 module, Alex Freed
• Xilinx ISE Passing IO pad attributes using UCF file., Andrew FPGA
  • Re: Xilinx ISE Passing IO pad attributes using UCF file., Bob Perlman
    • Re: Xilinx ISE Passing IO pad attributes using UCF file., Andrew FPGA
• JTAG USB Circuit, fecs2
  • Re: JTAG USB Circuit, Al Clark
    • Re: JTAG USB Circuit, GPE
      • Message not available
      • Re: JTAG USB Circuit, janbeck
      • Message not available
      • Re: JTAG USB Circuit, GPE
• EDK libgen cc choice, praetorian
• XST equivelent for Synplify "synthesis syn_preserve = 1", Austin Franklin
  • Re: XST equivelent for Synplify "synthesis syn_preserve = 1", Austin Franklin
• OPB bus communication, Nitesh
  • Re: OPB bus communication, melbadri
    • Message not available
      • Re: OPB bus communication, Sylvain Munaut
      • Re: OPB bus communication, Nitesh
• Core import into ISE, Roger
  • Re: Core import into ISE, Duane Clark
    • Re: Core import into ISE, Roger
      • Re: Core import into ISE, Duane Clark
      • Re: Core import into ISE, Roger
• picoblaze IDE for Linux, M6
  • Re: picoblaze IDE for Linux, Stephane
  • Re: picoblaze IDE for Linux, francesco_poderico
    • Re: picoblaze IDE for Linux, M6
      • Re: picoblaze IDE for Linux, Adrian Knoth
      • Re: picoblaze IDE for Linux, M6
• SoC embedded FPGA, kagior
  • Re: SoC embedded FPGA, Zara
    • Re: SoC embedded FPGA, Joseph
  • Re: SoC embedded FPGA, Tom Twist
  • Re: SoC embedded FPGA, ningxue2000
  • Re: SoC embedded FPGA, ningxue2000
• problem with Thold violation under quartus, pinkotronic
  • Message not available
    • Re: problem with Thold violation under quartus, Peter Alfke
  • Re: problem with Thold violation under quartus, Subroto Datta
• program prom by the fpga, nahum_barnea
• xilinx ML310 board PCI DMA problem, laoshan.zb@xxxxxxxxx
  • Re: xilinx ML310 board PCI DMA problem, VB
• Simulation : EDK, EDK Simulation
• Reprogramming FPGA over PCI???, john . orlando
  • Re: Reprogramming FPGA over PCI???, Adrian Knoth
  • Re: Reprogramming FPGA over PCI???, Mark McDougall
  • Re: Reprogramming FPGA over PCI???, Kolja Sulimma
    • Re: Reprogramming FPGA over PCI???, nahum_barnea
  • Re: Reprogramming FPGA over PCI???, Nial Stewart
  • Re: Reprogramming FPGA over PCI???, Peter Wallace
    • Re: Reprogramming FPGA over PCI???, john . orlando
  • Re: Reprogramming FPGA over PCI???, Austin Franklin
  • Re: Reprogramming FPGA over PCI???, Petter Gustad
• ISE 7.1i incremental synthesis, bkuschak
  • Re: ISE 7.1i incremental synthesis, Stephan
    • Re: ISE 7.1i incremental synthesis, bkuschak@xxxxxxxxx
• Unknown price difference for xilinx fpga, Hahnsolo
  • Re: Unknown price difference for xilinx fpga, pipjockey
    • Re: Unknown price difference for xilinx fpga, Hahnsolo
• Two short-term research grants, Davide Anguita
• FPGA's in bulk and pricing, jai.dhar@xxxxxxxxx
  • <Possible follow-ups>
  • FPGA's in bulk and pricing, jai.dhar@xxxxxxxxx
    • Re: FPGA's in bulk and pricing, GMM50
      • Re: FPGA's in bulk and pricing, jai.dhar@xxxxxxxxx
• Reverse Engineering Output Files, Jock
  • Re: Reverse Engineering Output Files, Steven J. Hill
• modelsim, u_stadler@xxxxxxxx
• Using two PowerPCs, Frank van Eijkelenburg
• Generating Modelsim Verilog resource libraries - pointers/questions, Garrick
  • Re: Generating Modelsim Verilog resource libraries - pointers/questions, Kim Enkovaara
    • Re: Generating Modelsim Verilog resource libraries - pointers/questions, Garrick
      • Re: Generating Modelsim Verilog resource libraries - pointers/questions, Kim Enkovaara
      • Re: Generating Modelsim Verilog resource libraries - pointers/questions, Garrick
      • Re: Generating Modelsim Verilog resource libraries - pointers/questions, Garrick
      • Re: Generating Modelsim Verilog resource libraries - pointers/questions, Kim Enkovaara
• [PATCH] Xilinx Linux driver package clean-up., Steven J. Hill
• Dll device for FPGA, Le.Wang
  • Re: Dll device for FPGA, Alex
• Using BRAMs in VHDL on Virtex II FPGAs, mte01
  • Re: Using BRAMs in VHDL on Virtex II FPGAs, Paul Lee
  • Re: Using BRAMs in VHDL on Virtex II FPGAs, Mike Treseler
• Xilinx Wizard does not create vhdl DMA template?, Marco
• Insight / Xilinx Spartan II Demo Board files?, Pete Fraser
• Software tools for architectural diagrams and for timing diagram entry?, Telenochek
  • Re: Software tools for architectural diagrams and for timing diagram entry?, JJ
  • Re: Software tools for architectural diagrams and for timing diagram entry?, Mike Treseler
    • Re: Software tools for architectural diagrams and for timing diagram entry?, Telenochek
• Digilent USB2 module in B1 expansion slot, CMOS
• how to set OPB EMC for flash use?, athena
  • Re: how to set OPB EMC for flash use?, joe4702
  • Re: how to set OPB EMC for flash use?, Athena
    • Re: how to set OPB EMC for flash use?, Duane Clark
      • Re: how to set OPB EMC for flash use?, Duane Clark
  • Re: how to set OPB EMC for flash use?, Athena
• Looking for info on the V8/Arclite MicroRISC 8-bit core, radarman
• DEV_CLRn and CRC_ERROR on ALTERA Cyclone, alessandro . strazzero
  • Re: DEV_CLRn and CRC_ERROR on ALTERA Cyclone, Rob
• Interrupt Handling, Marco
• problem with programming avnet edk board over LPT, Sleep Mode
  • Re: problem with programming avnet edk board over LPT, Zara
    • Re: problem with programming avnet edk board over LPT, Sleep Mode
      • Re: problem with programming avnet edk board over LPT, Zara
      • Re: problem with programming avnet edk board over LPT, Yannis Koryfidis
      • Re: problem with programming avnet edk board over LPT, Sean Durkin
      • Re: problem with programming avnet edk board over LPT, Yannis Koryfidis
      • Re: problem with programming avnet edk board over LPT, Yannis Koryfidis
• DCM question, zoinks@xxxxxxxxxxxxxxx
  • Re: DCM question, Zara
  • Re: DCM question, Marc Randolph
  • Re: DCM question, John_H
  • Re: DCM question, Brad Smallridge
• ISE 7.1 on Linux, ngdbuild failed without error, Ashok
• flash on P160 Module, lina
• Xilinx ML403, Brad Smallridge
  • Re: Xilinx ML403, Ed McGettigan
    • Re: Xilinx ML403, Brad Smallridge
      • Re: Xilinx ML403, Martin Thompson
      • Re: Xilinx ML403, Brad Smallridge
      • Message not available
      • Re: Xilinx ML403, Brad Smallridge
      • Re: Xilinx ML403, Ed McGettigan
      • Re: Xilinx ML403, Brad Smallridge
• SDRAM HOW?, fahadislam2002
  • Re: SDRAM HOW?, Mike Harrison
    • Re: SDRAM HOW?, dlharmon
  • Re: SDRAM HOW?, Mike Harrison
  • re:SDRAM HOW?, Tony30
• Small (OEM-)Memory Modules (SRAM/FLASH/DRAM), Udo
  • Re: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM), JJ
  • Re: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM), Kolja Sulimma
    • Re: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM), Udo
• Starbridge Hypercomputer & Viva, Robin Bruce
  • Re: Starbridge Hypercomputer & Viva, c d saunter
• Xilinx V2Pro & SATA hard disk, Mancini Stephane
  • Re: Xilinx V2Pro & SATA hard disk, Ed McGettigan
• ISE 7.1 service packs, Nemesis
  • Re: ISE 7.1 service packs, Marco
• HAL fuse map organization issue, logjam
  • Re: HAL fuse map organization issue, logjam
• Matched Filter, faaizal
• Re: Address Decoder, Weddick
  • Re: Address Decoder, TTigger
• PCI configuration questions., Mike Zhang
  • Re: PCI configuration questions., Joel Kolstad
    • Re: PCI configuration questions., Mike
  • Re: PCI configuration questions., Kevin Brace
    • Re: PCI configuration questions., Mike
• IP Protection of code block in Xilinx FPGA?, Paul Urbanus
  • Message not available
    • Message not available
      • Re: IP Protection of code block in Xilinx FPGA?, Martin Thompson
  • Re: IP Protection of code block in Xilinx FPGA?, Alvin Andries
• Re: VHDL: Address Decoder, Mike Treseler
  • Re: VHDL: Address Decoder, Symon
  • Re: VHDL: Address Decoder, Weddick
• USB tranciever + controller in FPGA, Eric
  • Re: USB tranciever + controller in FPGA, johnp
  • Re: USB tranciever + controller in FPGA, John M
• TAP controller, DIGONNET Daniel
• FFT implementation in Xilinx Spartan 3 started kit, biot
  • Re: FFT implementation in Xilinx Spartan 3 started kit, Aurelian Lazarut
  • Re: FFT implementation in Xilinx Spartan 3 started kit, Vladislav Muravin
    • Re: FFT implementation in Xilinx Spartan 3 started kit, biot
      • Re: FFT implementation in Xilinx Spartan 3 started kit, Vladislav Muravin
      • Re: FFT implementation in Xilinx Spartan 3 started kit, Dave
      • Re: FFT implementation in Xilinx Spartan 3 started kit, biot
  • Re: FFT implementation in Xilinx Spartan 3 started kit, Eric
• ARM IP Core implementation in FPGA, sudarangareddy
  • Re: ARM IP Core implementation in FPGA, Joseph
• fan out capability of FPGA, vssumesh
  • Re: fan out capability of FPGA, Mark McDougall
    • Re: fan out capability of FPGA, Mark McDougall
  • Re: fan out capability of FPGA, Kolja Sulimma
  • Re: fan out capability of FPGA, Vladislav Muravin
    • Re: fan out capability of FPGA, vssumesh
      • Re: fan out capability of FPGA, Ed McGettigan
• XilinX MAC FIR, seb_tech_fr
  • Re: XilinX MAC FIR, Ben Jones
  • Re: XilinX MAC FIR, John McCluskey
  • re:XilinX MAC FIR, seb_tech_fr
• Is a CPLD appropriate for this triple PWM application?, they call me frenchy
  • Re: Is a CPLD appropriate for this triple PWM application?, Luis Cupido
    • Message not available
      • Re: Is a CPLD appropriate for this triple PWM application?, Luis Cupido
      • Message not available
      • Message not available
      • Message not available
      • Re: Is a CPLD appropriate for this triple PWM application?, Falk Brunner
      • Re: Is a CPLD appropriate for this triple PWM application?, they call me frenchy
      • Re: Is a CPLD appropriate for this triple PWM application?, Falk Brunner
      • Re: Is a CPLD appropriate for this triple PWM application?, they call me frenchy
      • Re: Is a CPLD appropriate for this triple PWM application?, Jim Granville
  • Message not available
    • Re: Is a CPLD appropriate for this triple PWM application?, they call me frenchy
      • Re: Is a CPLD appropriate for this triple PWM application?, Jim Granville
      • Re: Is a CPLD appropriate for this triple PWM application?, they call me frenchy
      • Re: Is a CPLD appropriate for this triple PWM application?, David Brown
      • Re: Is a CPLD appropriate for this triple PWM application?, they call me frenchy
      • Re: Is a CPLD appropriate for this triple PWM application?, Jim Granville
      • Re: Is a CPLD appropriate for this triple PWM application?, David Brown
      • Re: Is a CPLD appropriate for this triple PWM application?, they call me frenchy
      • Re: Is a CPLD appropriate for this triple PWM application?, David Brown
  • Re: Is a CPLD appropriate for this triple PWM application?, they call me frenchy
    • Re: Is a CPLD appropriate for this triple PWM application?, Gabor
      • Re: Is a CPLD appropriate for this triple PWM application?, kevinjwhite
• edk service pack download, bassos
• FIFO design using Virtex-II block ram.., Remco
  • Re: FIFO design using Virtex-II block ram.., John_H
  • Re: FIFO design using Virtex-II block ram.., Vladislav Muravin
    • Re: FIFO design using Virtex-II block ram.., Remco
      • Re: FIFO design using Virtex-II block ram.., Mike Treseler
      • Re: FIFO design using Virtex-II block ram.., Remco
• Spartan-3 1000 -5 availability, Finn S. Nielsen
  • Re: Spartan-3 1000 -5 availability, Simon Peacock
  • Re: Spartan-3 1000 -5 availability, Austin Lesea
• floppycontroller, Soenke
• 24 Counters on one board, Le.Wang
  • Re: 24 Counters on one board, Phil Hays
  • Re: 24 Counters on one board, Jim Granville
    • Re: 24 Counters on one board, Simon Peacock
  • Re: 24 Counters on one board, Le.Wang
• Migration Altera APEX20KE to ???, Manfred Balik
  • Re: Migration Altera APEX20KE to ???, Daniel Lang
  • Re: Migration Altera APEX20KE to ???, htoerrin
    • Message not available
      • Re: Migration Altera APEX20KE to ???, Vaughn Betz
• Tree Representation of Logic Circuits, apsolar
  • Re: Tree Representation of Logic Circuits, Ulrich Bangert
• CPU benchmark for Xilinx PAR, Paul Gentieu
  • Re: CPU benchmark for Xilinx PAR, John Adair
  • Re: CPU benchmark for Xilinx PAR, JJ
  • Re: CPU benchmark for Xilinx PAR, B. Joshua Rosen
    • Re: CPU benchmark for Xilinx PAR, concerned_altera
  • Re: CPU benchmark for Xilinx PAR, Vladislav Muravin
  • Re: CPU benchmark for Xilinx PAR, B. Joshua Rosen
    • Re: CPU benchmark for Xilinx PAR, Brannon
    • Re: CPU benchmark for Xilinx PAR, John_H
      • Re: CPU benchmark for Xilinx PAR, Bret Wade
• P&R speed higher than synthesis, Adrian
  • Re: P&R speed higher than synthesis, JJ
• FFT implementation in Xilinx's Spartan 3, biot
  • Re: FFT implementation in Xilinx's Spartan 3, Zara
  • Re: FFT implementation in Xilinx's Spartan 3, Jens Baumann
    • Re: FFT implementation in Xilinx's Spartan 3, biot
• Please Help:Modelsim-Altera License "Verilog Computer Based training course", junnuthula
• Microblaze & Memory DMA operation, Ram
  • Re: Microblaze & Memory DMA operation, Adrian Knoth
  • Re: Microblaze & Memory DMA operation, Göran Bilski
    • Re: Microblaze & Memory DMA operation, Ram
      • Re: Microblaze & Memory DMA operation, Göran Bilski
      • Re: Microblaze & Memory DMA operation, Ram
      • Re: Microblaze & Memory DMA operation, Göran Bilski
  • Re: Microblaze & Memory DMA operation, Terry Fowler
    • Re: Microblaze & Memory DMA operation, Zara
      • Re: Microblaze & Memory DMA operation, Terry Fowler
      • Re: Microblaze & Memory DMA operation, Zara
    • Re: Microblaze & Memory DMA operation, Göran Bilski
• ISE 7.1i & Linux / reg code question, Ram
  • Re: ISE 7.1i & Linux / reg code question, Adrian Knoth
  • Re: ISE 7.1i & Linux / reg code question, Duane Clark
  • Re: ISE 7.1i & Linux / reg code question, Jim Wu
    • Re: ISE 7.1i & Linux / reg code question, Ram
      • Re: ISE 7.1i & Linux / reg code question, B. Joshua Rosen
      • Re: ISE 7.1i & Linux / reg code question, Ram
      • Re: ISE 7.1i & Linux / reg code question, John McCluskey
      • Re: ISE 7.1i & Linux / reg code question, kmlpatel@xxxxxxxxx
  • <Possible follow-ups>
  • ISE 7.1i & Linux / reg code question, Ram
    • Re: ISE 7.1i & Linux / reg code question, Adrian Knoth
• reducing the number of IOBS in a design, geoffrey wall
  • Re: reducing the number of IOBS in a design, John_H
  • Re: reducing the number of IOBS in a design, Jim Wu
  • Re: reducing the number of IOBS in a design, Vladislav Muravin
• modelsim simulation problem, Nitesh
  • Re: modelsim simulation problem, Sean Durkin
    • Re: modelsim simulation problem, Nitesh
• Xilkernel problem, adrian
• xilinx ise / update schematics, walter zabel
• place and route, GaLaKtIkUs?
  • Re: place and route, Sven
  • Re: place and route, Phil Hays
  • Re: place and route, GaLaKtIkUs?
    • Re: place and route, Sven
    • Re: place and route, Austin Lesea
      • Re: place and route, Sven
      • Re: place and route, GaLaKtIkUs?
• Fatal errror in ISE 6.3 i, stud_lang_jap
  • Re: Fatal errror in ISE 6.3 i, Sean Durkin
  • Re: Fatal errror in ISE 6.3 i, Vladislav Muravin
    • Re: Fatal errror in ISE 6.3 i, stud_lang_jap
• SDRAM quality, Jon Schneider
  • Re: SDRAM quality, Hiding in Plain Sight
    • Re: SDRAM quality, Aurelian Lazarut
  • Re: SDRAM quality, Mike Harrison
  • Re: SDRAM quality, Mark McDougall
    • Re: SDRAM quality, jai.dhar@xxxxxxxxx
      • Re: SDRAM quality, Mark McDougall
  • Re: SDRAM quality, Alvin Andries
    • Re: SDRAM quality, Mike Harrison
• several ucf files?, Stephane
  • Re: several ucf files?, allanherriman
• Block RAM problem (spartan 3), ni . neofpga
• Which JTAG cable for Xilinx & Linux?, Ram
  • Re: Which JTAG cable for Xilinx & Linux?, Grahame Kelly
  • Re: Which JTAG cable for Xilinx & Linux?, Neil Glenn Jacobson
    • Re: Which JTAG cable for Xilinx & Linux?, Zara
• future of antifuse fpgas?, Adam Megacz
  • Re: future of antifuse fpgas?, austin
    • Re: future of antifuse fpgas?, Adam Megacz
      • Re: future of antifuse fpgas?, Philip Freidin
      • Re: future of antifuse fpgas?, Adam Megacz
      • Message not available
      • Re: future of antifuse fpgas?, austin
    • Re: future of antifuse fpgas?, Thomas Womack
• creating a custom opb bus master, arincm@xxxxxxxxxxx
  • Re: creating a custom opb bus master, alan
  • Re: creating a custom opb bus master, Paul Hartke
  • Re: creating a custom opb bus master, beeraka@xxxxxxxxx
• Need advice: old Xilinx schematic design -> VHDL...GSR issue(s), Bob Myers
  • Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s), Mike Treseler
  • Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s), Duane Clark
    • Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s), Bob Myers
      • Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s), Bob Myers
• compedklib error, Nitesh
• implementing the tristate bus, stud_lang_jap
  • Re: implementing the tristate bus, Vladislav Muravin
    • Re: implementing the tristate bus, stud_lang_jap
      • Re: implementing the tristate bus, vssumesh
• Has anyone successfully used opencores PCI in FPGA desings?, Robert
  • Re: Has anyone successfully used opencores PCI in FPGA desings?, Kevin Brace
  • Re: Has anyone successfully used opencores PCI in FPGA desings?, Mark McDougall
  • Re: Has anyone successfully used opencores PCI in FPGA desings?, John McCaskill
• Post synthesis simulation errors, Giox
  • Re: Post synthesis simulation errors, Mike Treseler
    • Re: Post synthesis simulation errors, johnp
  • Re: Post synthesis simulation errors, Phil Hays
    • Re: Post synthesis simulation errors, Giox
      • Re: Post synthesis simulation errors, Phil Hays
      • Re: Post synthesis simulation errors, Giox
  • Re: Post synthesis simulation errors, Pasacco
    • Re: Post synthesis simulation errors, Giox
• Reading a PAL fusemap with a microscope, logjam
  • Re: Reading a PAL fusemap with a microscope, logjam
    • Re: Reading a PAL fusemap with a microscope, logjam
      • Re: Reading a PAL fusemap with a microscope, logjam
      • Re: Reading a PAL fusemap with a microscope, Gabor
      • Re: Reading a PAL fusemap with a microscope, Marc Reinig
      • Re: Reading a PAL fusemap with a microscope, Jim Granville
      • Re: Reading a PAL fusemap with a microscope, logjam
      • Re: Reading a PAL fusemap with a microscope, Philip Freidin
      • Re: Reading a PAL fusemap with a microscope, logjam
      • Re: Reading a PAL fusemap with a microscope, Alex Freed
      • Re: Reading a PAL fusemap with a microscope, logjam
      • Re: Reading a PAL fusemap with a microscope, logjam
      • Re: Reading a PAL fusemap with a microscope, Jim Granville
      • Re: Reading a PAL fusemap with a microscope, Ram
      • Re: Reading a PAL fusemap with a microscope, Alex Freed
• Timing Violation Quartus "__Z" issue, archilleswaterland@xxxxxxxxxxx
• EDK 7.1 simulation, Nitesh
• Microblaze and LMB, Zara
  • Re: Microblaze and LMB, Paul Hartke
    • Re: Microblaze and LMB, Zara
• digilent web site?, Pete Fraser
  • Re: digilent web site?, Paul Hartke
• Quartus II - Timing Analyzer, sanjay . gajendra
  • Re: Quartus II - Timing Analyzer, Mark McDougall
    • Re: Quartus II - Timing Analyzer, Subroto Datta
• xilinx virtex 2 multimedia board ( XC2V2000), mike
• [XST] FSM extraction question, Tim Verstraete
  • Re: FSM extraction question, Tim Verstraete
  • Re: [XST] FSM extraction question, Mike Treseler
    • Re: FSM extraction question, ALuPin
    • Re: FSM extraction question, ALuPin
• ML361 Documentation...., henrique . portela
  • Re: ML361 Documentation...., Ben Jones
    • Re: ML361 Documentation...., henrique . portela
• burn xcf16p through PCI jtag, nahum_barnea
• Re: Bootloading with flash-config devices, brendan . rankin
• pll, Designfreek
• Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;, glen herrmannsfeldt
  • Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;, Subroto Datta
    • Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;, glen herrmannsfeldt
  • <Possible follow-ups>
  • Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;, glen herrmannsfeldt
• Re: Best FPGA for floating point performance, glen herrmannsfeldt
  • <Possible follow-ups>
  • Re: Best FPGA for floating point performance, glen herrmannsfeldt
• Re: 8087 co-processor, glen herrmannsfeldt
• RocketIO code example, Roger
  • Re: RocketIO code example, Duane Clark
    • Re: RocketIO code example, Roger
• ISE7.1 SP4: proble and chipscope problem, Tim Verstraete
  • Re: ISE7.1 SP4: proble and chipscope problem, Duane Clark
• chipscope/core implementation, Gardovan
• re:chipscope and V2P problems, Gardovan
• ISE 64bit question, Matthew Plante
  • Re: ISE 64bit question, aholtzma
  • Re: ISE 64bit question, Hiding in Plain Sight
  • Re: ISE 64bit question, mk
• used boards? cache design? DDR2 controller?, Tony30
• Help finding Signetics Datasheets, logjam
  • Re: Help finding Signetics Datasheets, logjam
• OpenTech open source designs and tools, jamilkhatib75
• to use flash on the fpga board, Lina
  • Re: to use flash on the fpga board, Lina
    • Re: to use flash on the fpga board, Newman
• Signed addition, news.green.ch
  • Re: Signed addition, Sylvain Munaut
    • Re: Signed addition, Simon Peacock
      • Re: Signed addition, Sylvain Munaut
      • Re: Signed addition, Peter Harrison
      • Re: Signed addition, Simon Peacock
  • Re: Signed addition, Paulo Dutra
  • Re: Signed addition, Marko
    • Re: Signed addition, Simon Peacock
• Re: openrisc, jp1 jtag debug utility, jeff murphy
• Spartan-3E Starter Kit availability slips to December, Eric Smith
  • Re: Spartan-3E Starter Kit availability slips to December, Mike Harrison
    • Re: Spartan-3E Starter Kit availability slips to December, jcarr@xxxxxxxxxxxxxxxxx
      • Re: Spartan-3E Starter Kit availability slips to December, Mike Treseler
      • Re: Spartan-3E Starter Kit availability slips to December, Duane Clark
      • Re: Spartan-3E Starter Kit availability slips to December, Phil Tomson
  • Re: Spartan-3E Starter Kit availability slips to December, Alex Gibson
• Linux on Viretex-II pro, Eric
  • Re: Linux on Viretex-II pro, Peter Ryser
• spartan 3 starter kit auto configuration at power up, CMOS
  • Re: spartan 3 starter kit auto configuration at power up, Brad Smallridge
  • Re: spartan 3 starter kit auto configuration at power up, Marco
• WARNING:HDLParsers:3481 - No primary, secondary unit in the file, Brad Smallridge
• Cyclone conf flash - 25p10 !, Luis Cupido
  • Message not available
    • Message not available
      • Re: Cyclone conf flash - 25p10 !, jai.dhar@xxxxxxxxx
      • Re: Cyclone conf flash - 25p10 !, Luis Cupido
  • Message not available
    • Message not available
      • Message not available
      • Re: Cyclone conf flash - 25p10 !, Jim Granville
      • Re: Cyclone conf flash - 25p10 !, jai.dhar@xxxxxxxxx
      • Re: Cyclone conf flash - 25p10 !, Jim Granville
      • Re: Cyclone conf flash - 25p10 !, Mark McDougall
      • Re: Cyclone conf flash - 25p10 !, Al Clark
      • Re: Cyclone conf flash - 25p10 !, Mark McDougall
      • Re: Cyclone conf flash - 25p10 !, jai.dhar@xxxxxxxxx
      • Re: Cyclone conf flash - 25p10 !, Al Clark
      • Re: Cyclone conf flash - 25p10 !, jai.dhar@xxxxxxxxx
      • Re: Cyclone conf flash - 25p10 !, Al Clark
      • Re: Cyclone conf flash - 25p10 !, Nial Stewart
      • Re: Cyclone conf flash - 25p10 !, jai.dhar@xxxxxxxxx
      • Re: Cyclone conf flash - 25p10 !, Luis Cupido
• Any GOSPL Docs?, Andrew Greensted
• ANN: Altera Power Net Seminar #2, Paul Leventis \(at home\)
  • Re: Altera Power Net Seminar #2, Paul Leventis \(at home\)
    • Re: Altera Power Net Seminar #2, che_fong
• SI newsgroup, blah
  • Re: SI newsgroup, MM
• Partial vector range in instance warning, Newman
  • Re: Partial vector range in instance warning, Newman
• Spartan 3E and Spartan 3 with GTL, Sima
• PCI on ML310 Xilinx board, Sven Gowal
  • Re: PCI on ML310 Xilinx board, Peter Ryser
    • Re: PCI on ML310 Xilinx board, Sven Gowal
      • Re: PCI on ML310 Xilinx board, Paul Hartke
      • Re: PCI on ML310 Xilinx board, Sven Gowal
• SPARATAN 2E - input clock, amko
  • Re: SPARATAN 2E - input clock, I. Ulises Hernandez
• Disconnect the FPGA I/O pads from the outside world, vssumesh
  • Re: Disconnect the FPGA I/O pads from the outside world, pipjockey
    • Re: Disconnect the FPGA I/O pads from the outside world, vssumesh
      • Re: Disconnect the FPGA I/O pads from the outside world, Matthieu Michon
      • Re: Disconnect the FPGA I/O pads from the outside world, vssumesh
      • Re: Disconnect the FPGA I/O pads from the outside world, dfx
• Carry saver adder, mehul
• Quartus2 WEB: Simulating from test bench. Is that possible?, Andre G.
  • Re: Quartus2 WEB: Simulating from test bench. Is that possible?, ALuPin
    • Re: Quartus2 WEB: Simulating from test bench. Is that possible?, ALuPin
• Re: TTL, CMOS and spartan, dlharmon
• Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed.", VSP
  • Re: Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed.", Zara
  • Re: Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed.", Duane Clark
• Area Estimation Issues, skatoulas
• PPC405 32 bit aligned accesses, I. Ulises Hernandez
  • Re: PPC405 32 bit aligned accesses, Symon
    • Re: PPC405 32 bit aligned accesses, I. Ulises Hernandez
      • Re: PPC405 32 bit aligned accesses, Symon
      • Re: PPC405 32 bit aligned accesses, Kolja Sulimma
      • Re: PPC405 32 bit aligned accesses, I. Ulises Hernandez
      • Re: PPC405 32 bit aligned accesses, Peter Ryser
      • Re: PPC405 32 bit aligned accesses, I. Ulises Hernandez
      • Re: PPC405 32 bit aligned accesses, Symon
      • Re: PPC405 32 bit aligned accesses, Peter Ryser
      • Re: PPC405 32 bit aligned accesses, Symon
      • Re: PPC405 32 bit aligned accesses, Peter Ryser
      • Re: PPC405 32 bit aligned accesses, I. Ulises Hernandez
      • Re: PPC405 32 bit aligned accesses, Symon
      • Re: PPC405 32 bit aligned accesses, Peter Ryser
      • Re: PPC405 32 bit aligned accesses, Peter Ryser
• False values in Quartus In-System Memory Editor, Sebastian Schmidt
  • Re: False values in Quartus In-System Memory Editor, ALuPin
    • Re: False values in Quartus In-System Memory Editor, Sebastian Schmidt
      • Re: False values in Quartus In-System Memory Editor, ALuPin
      • Re: False values in Quartus In-System Memory Editor, Sebastian Schmidt
      • Re: False values in Quartus In-System Memory Editor, ALuPin
      • Re: False values in Quartus In-System Memory Editor, Sebastian Schmidt
• Nand Flash Emulator, Gromer
• Fastest input IOB on a Spartan-3?, Paul Boven
  • Re: Fastest input IOB on a Spartan-3?, Symon
    • Re: Fastest input IOB on a Spartan-3?, Austin Lesea
      • Re: Fastest input IOB on a Spartan-3?, Symon
      • Re: Fastest input IOB on a Spartan-3?, Austin Lesea
      • Re: Fastest input IOB on a Spartan-3?, Symon
      • Re: Fastest input IOB on a Spartan-3?, austin
      • Re: Fastest input IOB on a Spartan-3?, Brian Davis
      • Re: Fastest input IOB on a Spartan-3?, austin
• Defining Environment variables inside EDK, Sylvain Munaut
  • Re: Defining Environment variables inside EDK, Amit Kasat
    • Re: Defining Environment variables inside EDK, Sylvain Munaut
• Reprogramming one MAXII EPM1270 vs security bit set, abeaujean@xxxxxxxxxxxxx
  • Re: Reprogramming one MAXII EPM1270 vs security bit set, Luis Cupido
    • Re: Reprogramming one MAXII EPM1270 vs security bit set, joe . delaere
• Reading internal signals through a testbench., CODE_IS_BAD
  • Re: Reading internal signals through a testbench., ALuPin
    • Re: Reading internal signals through a testbench., Andrew FPGA
      • Re: Reading internal signals through a testbench., Jeff Cunningham
      • Re: Reading internal signals through a testbench., Gabor
• coe file of Xilinx MAC FIR core??, AdamS
  • Re: coe file of Xilinx MAC FIR core??, Johan Bernspång
• Problem with interfacingT-VPACK with ALTERA QUIP5.0, Narayan
  • Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0, raj
  • Message not available
    • Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0, Narayan
• Quartus web edition simulation with off-chip logic?, VAX9000
• Partial Reconfiguration : New Forum, Michael
  • Re: Partial Reconfiguration : New Forum, Paul Hartke
• Logic??, Kumar
  • Re: Logic??, vizziee
    • Re: Logic??, Kumar
      • Re: Logic??, Slurp
  • Re: Logic??, John_H
  • Re: Logic??, Aurelian Lazarut
    • Re: Logic??, Kumar
• IC design contract, cell_rx
• Long Multiplication, Gary Pace
  • Re: Long Multiplication, Symon
    • Re: Long Multiplication, Gary Pace
• Modelling latches in Verilog, Philip Pemberton
  • Re: Modelling latches in Verilog, mk
    • Re: Modelling latches in Verilog, Philip Pemberton
• The best way to sum 8 datas?, Marco
  • Re: The best way to sum 8 datas?, Slurp
    • Re: The best way to sum 8 datas?, Marco
• Re: Digilent's JTAG-USB cable with chipscope, James Horn
• Platform Cable USB, Roger
  • Re: Platform Cable USB, James Horn
    • Re: Platform Cable USB, Roger
• Spartan 3 Ram Instantiation, amir . intisar
  • Re: Spartan 3 Ram Instantiation, Falk Brunner
  • Re: Spartan 3 Ram Instantiation, John_H
    • Re: Spartan 3 Ram Instantiation, amir . intisar
      • Re: Spartan 3 Ram Instantiation, Philip Freidin
      • Re: Spartan 3 Ram Instantiation, John_H
      • Re: Spartan 3 Ram Instantiation, amir . intisar
      • Re: Spartan 3 Ram Instantiation, John_H
  • Re: Spartan 3 Ram Instantiation, Brad Smallridge
• gal16v8 CUPL problems, Lathe_Biosas
  • Re: gal16v8 CUPL problems, Jim Granville
• SI considerations for single chip memory configurations, Marc Battyani
  • Re: SI considerations for single chip memory configurations, John_H
• Re: Problem with ModelSim XE, G
• Re: LCD Interface, Falk Brunner
• Creating higher bit multipliers from low bit., vssumesh
  • Re: Creating higher bit multipliers from low bit., Ray Andraka
    • Re: Creating higher bit multipliers from low bit., Richard Carey
• XUP Virtex-II Pro "invalid target architecture", zoinks@xxxxxxxxxxxxxxx
  • Re: XUP Virtex-II Pro "invalid target architecture", Paul Hartke
  • Re: XUP Virtex-II Pro "invalid target architecture", Alex Gibson
    • Re: XUP Virtex-II Pro "invalid target architecture", zoinks@xxxxxxxxxxxxxxx
      • Re: XUP Virtex-II Pro "invalid target architecture", zoinks@xxxxxxxxxxxxxxx
      • Re: XUP Virtex-II Pro "invalid target architecture", Paul Hartke
      • Re: XUP Virtex-II Pro "invalid target architecture", Alex Gibson
      • Re: XUP Virtex-II Pro "invalid target architecture", zoinks@xxxxxxxxxxxxxxx
      • Re: XUP Virtex-II Pro "invalid target architecture", Paul Hartke
      • Re: XUP Virtex-II Pro "invalid target architecture", zoinks@xxxxxxxxxxxxxxx
• Modelsim simulation question, Marco
• Multidimensional port., vssumesh
  • Re: Multidimensional port., John_H
    • Re: Multidimensional port., vssumesh
      • Re: Multidimensional port., allanherriman
• Re: Embedded Processors/Serdes, Petter Gustad
  • Re: Embedded Processors/Serdes, Ed McGettigan
• Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3, Kris Heyrman
  • Re: Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3, S.T.
    • Re: Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3, Paul Hartke
      • Re: Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3, S.T.
• OT: CPLD - SimuCAD S/W CD, Gra
  • Re: CPLD - SimuCAD S/W CD, John_H
    • Re: CPLD - SimuCAD S/W CD, gallen
    • Re: CPLD - SimuCAD S/W CD, gallen
    • Re: CPLD - SimuCAD S/W CD, Grahame Kelly
      • Re: CPLD - SimuCAD S/W CD, Antonio Pasini
• I2C "SCL" line problem, praveen . kantharajapura
  • Re: I2C "SCL" line problem, alan
    • Re: I2C "SCL" line problem, Falk Brunner
      • Re: I2C "SCL" line problem, praveen . kantharajapura
      • Re: I2C "SCL" line problem, Jim Granville
      • Re: I2C "SCL" line problem, John_H
  • Re: I2C "SCL" line problem, Brad Smallridge
• Xilinx and Lattice tools on one machine?, Gabor
  • Re: Xilinx and Lattice tools on one machine?, troy . scott
• Modelsim XE and multi-file Verilog projects, Philip Pemberton
  • Re: Modelsim XE and multi-file Verilog projects, TD
  • Re: Modelsim XE and multi-file Verilog projects, Marko
    • Re: Modelsim XE and multi-file Verilog projects, gallen
      • Re: Modelsim XE and multi-file Verilog projects, johnp
• FIFO PhysDesignRules:993, Matthew Plante
• Xilinx Virtex II fpga - providing single ended signal to lvds defined pin, TD
• current!, John Larkin
  • Re: current!, John_H
    • Re: current!, John Larkin
      • Re: current!, John_H
• Re: Lot of 60 XCV1000 FPGAs, Vladislav Muravin
  • Re: Lot of 60 XCV1000 FPGAs, Ram
    • Re: Lot of 60 XCV1000 FPGAs, Ray Andraka
      • Re: Lot of 60 XCV1000 FPGAs, John Adair
• Spartan3 PCI SSO(Simultaneously Switching Output) problem, huangjie
  • Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem, John_H
    • Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem, huangjie
      • Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem, Austin Lesea
      • Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem, John_H
      • Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem, huangjie
      • Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem, Austin Lesea
      • Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem, John_H
      • Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem, huangjie
      • Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem, huangjie
      • Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem, huangjie
  • Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem, dfx
• Strange behaviour while trying to program MAX II CPLD's, abeaujean@xxxxxxxxxxxxx
  • Re: Strange behaviour while trying to program MAX II CPLD's, Paul Leventis \(at home\)
• Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform level signal connect., zoinks@xxxxxxxxxxxxxxx
  • Re: Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform level signal connect., Paul Hartke
    • Re: Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform level signal connect., zoinks@xxxxxxxxxxxxxxx
• Re: DCM does not do anything?, zoinks@xxxxxxxxxxxxxxx
  • <Possible follow-ups>
  • Re: DCM does not do anything?, zoinks@xxxxxxxxxxxxxxx
• "Perform Timing-Driven Packing and Placement" error?, Martin
  • Re: "Perform Timing-Driven Packing and Placement" error?, Ben Jones
    • Re: "Perform Timing-Driven Packing and Placement" error?, Ray Andraka
      • Re: "Perform Timing-Driven Packing and Placement" error?, Martin
    • Re: "Perform Timing-Driven Packing and Placement" error?, Martin
• New FPGA development board., Ian Muncaster
• A strange behavior, Marco
  • Re: A strange behavior, John_H
    • Re: A strange behavior, Marco
• bare die (non packaged) FPGA, CPLD, controllers ?, Dix
  • Re: bare die (non packaged) FPGA, CPLD, controllers ?, Daniel Leu
    • Re: bare die (non packaged) FPGA, CPLD, controllers ?, Dix
      • Re: bare die (non packaged) FPGA, CPLD, controllers ?, Jon Beniston
      • Re: bare die (non packaged) FPGA, CPLD, controllers ?, Dix
• CPLD CoolRunner-II - IO current limited to 8mA?, denizdikmen
  • Re: CPLD CoolRunner-II - IO current limited to 8mA?, Aurelian Lazarut
  • Re: CPLD CoolRunner-II - IO current limited to 8mA?, Falk Brunner
  • Re: CPLD CoolRunner-II - IO current limited to 8mA?, John Adair
  • Re: CPLD CoolRunner-II - IO current limited to 8mA?, Jim Granville
• Discrepancies in area estimation (Precision RTL vs Xilinx ISE Map), giachella . g
  • Re: Discrepancies in area estimation (Precision RTL vs Xilinx ISE Map), Aurelian Lazarut
• Mentor FPGA Advantage, a simple question, ciappalastringa
  • Re: Mentor FPGA Advantage, a simple question, Mike Treseler
    • Re: Mentor FPGA Advantage, a simple question, ciappalastringa
• Re: usb and xc95, Marc Reinig
• Re: xilinx or digilent, Eric Smith
• Re: FPGA Development Board Wish List, Eric Smith
  • Re: FPGA Development Board Wish List, John Adair
• Re: Welcome back Mr. Knapp, Eric Smith
• New PCI Express Group, Mark
• Spartan 3 Serdes, Brad Smallridge
  • Re: Spartan 3 Serdes, Mark
  • Re: Spartan 3 Serdes, Hiding in Plain Sight
  • Re: Spartan 3 Serdes, Rob
    • Re: Spartan 3 Serdes, Mark
      • Re: Spartan 3 Serdes, Marc Randolph
      • Re: Spartan 3 Serdes, Brad Smallridge
      • Re: Spartan 3 Serdes, Marc Randolph
• Re: Low Power RTL Design, Ray Andraka
  • <Possible follow-ups>
  • Re: Low Power RTL Design, Paul Leventis \(at home\)
• Spartan-3 LVDS driving TFT LCD panel..?, Mike Harrison
  • Re: Spartan-3 LVDS driving TFT LCD panel..?, Sylvain Munaut
    • Re: Spartan-3 LVDS driving TFT LCD panel..?, Mike Harrison
  • Re: Spartan-3 LVDS driving TFT LCD panel..?, Andrew Dyer
    • Re: Spartan-3 LVDS driving TFT LCD panel..?, Mike Harrison
  • Re: Spartan-3 LVDS driving TFT LCD panel..?, John Adair
• Re: Hi-Z input, Brad Smallridge
  • Re: Hi-Z input, Marco
    • Re: Hi-Z input, Eric
    • Re: Hi-Z input, Brad Smallridge
  • <Possible follow-ups>
  • Re: Hi-Z input, Andy Peters
    • Re: Hi-Z input, Marco
• Re: Hello A newbie to FPGA, Austin Lesea
• Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a, Mike Treseler
  • <Possible follow-ups>
  • Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a, Jiri Bucek
• Re: Fine grain vs. Coarse Grain Architectures, Martin Ellis
  • <Possible follow-ups>
  • Re: Fine grain vs. Coarse Grain Architectures, Mike Treseler
• Re: chipscope commands?, Ed McGettigan
• Re: ZIF press-fit socket for QFP FPGA packages, Philip Freidin
• Re: Gated clock for FPGA (verilog)???, johnp
  • <Possible follow-ups>
  • Re: Gated clock for FPGA (verilog)???, Bob Perlman
  • Re: Gated clock for FPGA (verilog)???, Vladislav Muravin

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