Re: how to reduce vga memory????????

On Fri, 19 Aug 2005 10:58:28 +1000, Mark McDougall <markm@xxxxxxxxx>
wrote:

>+<fahadislam2002 wrote:
>+<
>+<> Hi... first thanks for responding........ 1- From time slicing u
>+<> mean slicing between rows and colums or between a fixed no of pixels
>+<> ? 2- I m using HM62256ALP-8 ... and its speed is 80ns :( ...
>+<
>+<For 640x480, scanline time is 31.77us. At 4 bits/pixel, you need to
>+<fetch 320 bytes in that time, which gives you ~100ns per byte. You'd
>+<also need to pre-fetch a scanline on-chip since the actual dot clock is
>+<around 25.175MHz (2 pixels = 79ns).
>+<
>+<But then your SRAM bandwidth utilisation is approaching 100%, which
>+<leaves no time for the CPU to update the video memory. I suppose it
>+<would be possible to output interleaved VGA, and use every other
>+<scanline to allow the CPU to update video RAM, but that has other design
>+<implications.
>+<
>+<Not ideal... :(
>+<
>+<Regards,
>+<Mark
********

You can set the sram up in two banks of 8 bit width each. So that when
the video controller reads the sram it reads two bytes at a time, even
and odd address. The CPU can write to the ram in either 8 or 16 bit
mode. Then use IDMA. When the uP clock is low then the video circuit
accesses ram. When the uC clock is high then the uC acesses the ram.
This works well with processor speeds up to about 25 MHz. When using
dram you need to consider the dram cycle time, not access time, needs
to be half the CPU cycle time max.

An old technique used in 8 bit computers from the 80's.

80nS cycle time ram will put a maximum of 12.5 Mhz CPU speed. In
reality it would be better to run the CPU at 12 MHz for better margin.
This adds more complex circuits in addressing the ram. One needs to
multiplex the video and cpu addresses as well as data buss. Nothing
really to difficult that can't be done in a FPGA though.

james
.

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