Re: struggling with general digital design

"Telenochek" <interpasha@xxxxxxxxxxx> wrote in message
news:1122921800.476690.247230@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

> I am trying to design with state machines.
> For example there is a master FSM (finite state machine), which
> calls slave state-machines along the way, waits for them to end (via
> slave-busy signals) etc...
> Unfortunately this approach becomes very messy very quickly.

I think you should be able to fit it into a single, relatively simple, state
machine.

> I understand the breakdown into components when somebody else writes
> it, and I understand the code, and how everything is connected.
> The problem arises when I need to come up with all the control signals
> myself, and make sure the dynamics of the system is working ok.
>
> I think thats a digital design problem, rather than a coding problem.
> Coding is *relatively* easy when you have a clear design.

You should try thinking in terms of hardware. In other words your code
should be describing hardware rather than its abstract behaviour. The only
exception in my view is a state machine. When I write state machines I
usually think in behavioural terms first and then add details later.

Which FPGA are you designing for? If you are using Xilinx, I suggest that
you use their Core Generator and generate a simple dual port memory buffer.
It will create a VHDL component declaration and an instantiation template.
Look at the interface and read the data *** to understand what each of the
signals is for.

If you are still confused, I can probably share some code with you as I do
have some similar designs...

/Mikhail


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