comp.arch.fpga

Date Index

ZIF press-fit socket for QFP FPGA packages, dima2882
Problems on Xilinx FIR Core, AdamS
chipscope commands?, peer
Hi-Z input, Marco
- Re: Hi-Z input, Gabor
- Re: Hi-Z input, Eric
  - Re: Hi-Z input, Marco
modular design: can one use long lines, john
Low Power RTL Design, mhosni80
- Re: Low Power RTL Design, John Adair
- <Possible follow-ups>
- Low Power RTL Design, mhosni80
Virtex4 : Downloading error, Shakith
- Re: Virtex4 : Downloading error, Jason Wu
Version 5.0 of Quartus University Interface Program (for researchers & graduate students) Released, Vaughn Betz
Implementing PLL in Cyclone - Schematic entry, Len
- Re: Implementing PLL in Cyclone - Schematic entry, Len
usb and xc95, iml
- Re: usb and xc95, AdamS
Re: EDK core wrapping and include files, Nju Njoroge
LCD Interface, Pierre de Vos
- Re: LCD Interface, Sylvain Munaut
  - Re: LCD Interface, Pierre de Vos
    - Re: LCD Interface, Jan Panteltje
    - Re: LCD Interface, Simon Peacock
- Re: LCD Interface, Marco
Gated clock for FPGA (verilog)???, yijun_lily@xxxxxxxxx
- Re: Gated clock for FPGA (verilog)???, Aurelian Lazarut
- Re: Gated clock for FPGA (verilog)???, Gabor
Quick Xilinx KCPSM3 with verilog question., Paul Marciano
UDP problems with Xilinx EDK 7.1, jswestra77
- Re: UDP problems with Xilinx EDK 7.1, jswestra77
Fine grain vs. Coarse Grain Architectures, Alissobn Brito
- Re: Fine grain vs. Coarse Grain Architectures, JJ
- Re: Fine grain vs. Coarse Grain Architectures, Andy Peters
  - Re: Fine grain vs. Coarse Grain Architectures, Alissobn Brito
Embedded Processors/Serdes, blah
- Re: Embedded Processors/Serdes, Eric
  - Re: Embedded Processors/Serdes, Ed McGettigan
  - Re: Embedded Processors/Serdes, Ed McGettigan
- Re: Embedded Processors/Serdes, Ed McGettigan
- Re: Embedded Processors/Serdes, JJ
- Re: Embedded Processors/Serdes, Luc
  - Re: Embedded Processors/Serdes, Ed McGettigan
Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a, Brian C . Van Essen
- Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a, Duane Clark
- Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a, Mike Treseler
  - Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a, Brian C . Van Essen
    - Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a, Duane Clark
openrisc, jp1 jtag debug utility, jeff murphy
- Re: openrisc, jp1 jtag debug utility, Javier Castillo
  - Re: openrisc, jp1 jtag debug utility, jeff murphy
    - Re: openrisc, jp1 jtag debug utility, Javier Castillo
8087 co-processor, CMOS
- Re: 8087 co-processor, JJ
- Re: 8087 co-processor, Mike Treseler
Re: Array of slope A/Ds in FPGA?, Jim Granville
- <Possible follow-ups>
- Re: Array of slope A/Ds in FPGA?, Larry Doolittle
re:beginner [ query : resources and guidance for a newbie], Xizen
- <Possible follow-ups>
- beginner [ query : resources and guidance for a newbie], nitins
  - Re: beginner [ query : resources and guidance for a newbie], learnfpga
JTAG conifguration via USB, Martin Schoeberl
Checking the PCI master implemented in FPGA, praveenkumar1979
Monitor the internal signal of EDF using chipscope, stud_lang_jap
fast universal compression scheme and its implementation in VHDL, Jens Mander
- Re: fast universal compression scheme and its implementation in VHDL, Thomas Entner
- Re: fast universal compression scheme and its implementation in VHDL, Sylvain Munaut
Xilinx PC4 Download Cable, sonne123
- <Possible follow-ups>
- Xilinx PC4 Download Cable, sonne123
Altera nios-debug via JTAG, evan
digilent spartan 3 kit example project, CMOS
- Re: digilent spartan 3 kit example project, Martin Schoeberl
- re:digilent spartan 3 kit example project, Xizen
- Re: digilent spartan 3 kit example project, Alex Gibson
Bootloading with flash-config devices, jai.dhar@xxxxxxxxx
Maybe a very cool FPGA a throw away idea for Xilinx, cpu16x1832
Question about program and memory location, Marco
mails from Aman Mediratta, Thomas Entner
- Re: mails from Aman Mediratta, Falk Brunner
  - Re: mails from Aman Mediratta, Jeff Cunningham
  - Re: mails from Aman Mediratta, Thomas Entner
  - Re: mails from Aman Mediratta, Marco
- Re: mails from Aman Mediratta, austin
- Re: mails from Aman Mediratta, John Adair
- Re: mails from Aman Mediratta, Philip Freidin
- Re: mails from Aman Mediratta, Hal Murray
  - Re: mails from Aman Mediratta, Benjamin Todd
How to reduce software size?, Marco
Altera Avalon Master/Slave User Defined Logic?, pinod01
Feedback signal cancellation algorithm, eeh
connecting block ram to datapath using bidirectional lines, Xizen
Clock skew in FPGA Xilinx?, yijun_lily@xxxxxxxxx
- Re: Clock skew in FPGA Xilinx?, mk
- Re: Clock skew in FPGA Xilinx?, Vladislav Muravin
Should I use DCM for every FPGA design?, yijun_lily@xxxxxxxxx
- Re: Should I use DCM for every FPGA design?, yijun_lily@xxxxxxxxx
  - Re: Should I use DCM for every FPGA design?, Simon Peacock
  - Re: Should I use DCM for every FPGA design?, Vladislav Muravin
Mark to initialize BRAM, Marco
Problem with ModelSim XE, learnfpga
- Re: Problem with ModelSim XE, Fpga_Designer
  - Re: Problem with ModelSim XE, learnfpga
    - Re: Problem with ModelSim XE, Fpga_Designer
    - Re: Problem with ModelSim XE, learnfpga
    - Re: Problem with ModelSim XE, Fpga_Designer
    - Re: Problem with ModelSim XE, Mike Treseler
36x36 signed multiplier?, Bubba
- Re: 36x36 signed multiplier?, Thomas Entner
  - Re: 36x36 signed multiplier?, Bubba
- Re: 36x36 signed multiplier?, Sylvain Munaut
- Re: 36x36 signed multiplier?, Ray Andraka
infering a BRAM block for a dual ported ROM, abgoyal
- Re: infering a BRAM block for a dual ported ROM, Marc Randolph
  - Re: infering a BRAM block for a dual ported ROM, Mike Treseler
    - Re: infering a BRAM block for a dual ported ROM, abgoyal
    - Re: infering a BRAM block for a dual ported ROM, Marc Randolph
SERDES, Rob
- Re: SERDES, Marc Randolph
  - Re: SERDES, Rob
ISE 7.1 and DCM clkfx, Matthew Plante
- Re: ISE 7.1 and DCM clkfx, Marc Randolph
Altera NIOS in a Cyclone, GMM50
Phase Offset in Xilinx DDS Core, AdamS
- Re: Phase Offset in Xilinx DDS Core, Falk Brunner
  - Re: Phase Offset in Xilinx DDS Core, AdamS
Writing to Spartan 3 SRAM, amir . intisar
- Re: Writing to Spartan 3 SRAM, Aurelian Lazarut
- Re: Writing to Spartan 3 SRAM, Eric
- Re: Writing to Spartan 3 SRAM, Vladislav Muravin
Bootloader Linker Script Help, Marco
SystemACE CF and partial reconfiguration, echoisme
Issues with Synplify Pro 7.7 synthesis, Harish Vutukuru
- Re: Issues with Synplify Pro 7.7 synthesis, John_H
  - Re: Issues with Synplify Pro 7.7 synthesis, Fpga_Designer
DMA issues with IPIF on V2P, el_boricua
On a different note: Unable to write edif files in Synopsys Design Compiler, anup
Re: Ones Count 64 bit on Xilinx in VHDL, glen herrmannsfeldt
- Re: Ones Count 64 bit on Xilinx in VHDL, Paul Marciano
Re: "Tbufs don't exist", glen herrmannsfeldt
i need some help ASAP !!! (DLL - Spartan-IIE), Vladislav Muravin
- Re: i need some help ASAP !!! (DLL - Spartan-IIE), johnp
  - Re: i need some help ASAP !!! (DLL - Spartan-IIE), AdamS
    - Re: i need some help ASAP !!! (DLL - Spartan-IIE), Vladislav Muravin
Altera ByteBlaster II vs ByteBlaster MV, abeaujean@xxxxxxxxxxxxx
- Re: Altera ByteBlaster II vs ByteBlaster MV, Ben Twijnstra
Microblaze Simple Bootloader, Marco
Library of eBooks on FPGA's and other programming stuff, Dimitri Turbiner
- Re: Library of eBooks on FPGA's and other programming stuff, Neo
- Re: Library of eBooks on FPGA's and other programming stuff, Jason Ozolins
- Re: Library of eBooks on FPGA's and other programming stuff, Ziggy
TTL, CMOS and spartan, CMOS
- Re: TTL, CMOS and spartan, Symon
- Re: TTL, CMOS and spartan, dlharmon
  - Re: TTL, CMOS and spartan, Sylvain Munaut
  - Re: TTL, CMOS and spartan, james
ADC Clock on Stratix II DSP Dev Board, Paul Solomon
- Re: ADC Clock on Stratix II DSP Dev Board, Vaughn Betz
Single PPC with DES on V2P, el_boricua
- Re: Single PPC with DES on V2P, Paul Hartke
  - Re: Single PPC with DES on V2P, el_boricua
    - Re: Single PPC with DES on V2P, Paul Hartke
    - Re: Single PPC with DES on V2P, el_boricua
Single PPC on Virtex 2 Pro DMA problems, el_boricua
- <Possible follow-ups>
- Single PPC on Virtex 2 Pro DMA problems, el_boricua
- Single PPC on Virtex 2 Pro DMA problems, el_boricua
Help coding a bigger project, Bubba
- Re: Help coding a bigger project, Vladislav Muravin
- Re: Help coding a bigger project, Mike Treseler
- Re: Help coding a bigger project, Simon Peacock
  - Re: Help coding a bigger project, Bubba
    - Re: Help coding a bigger project, Mike Treseler
fpga_editor and fvwm, Felix Madlener
Does LOCKED signal of Spartan3 DCM require clock to be de-asserted?, Wojtek2U
- Re: Does LOCKED signal of Spartan3 DCM require clock to be de-asserted?, Symon
- Re: Does LOCKED signal of Spartan3 DCM require clock to be de-asserted?, Alvin Andries
Spartan and Flash PROM : Boundary Scan, Pierre
- Re: Spartan and Flash PROM : Boundary Scan, Benjamin Todd
what is the difference between "configuring" and "programming"?, echoisme
- Re: what is the difference between "configuring" and "programming"?, huangjie
- Re: what is the difference between "configuring" and "programming"?, Symon
- Re: what is the difference between "configuring" and "programming"?, Neil Glenn Jacobson
  - Re: what is the difference between "configuring" and "programming"?, echoisme
    - Re: what is the difference between "configuring" and "programming"?, Symon
    - Re: what is the difference between "configuring" and "programming"?, austin
    - Re: what is the difference between "configuring" and "programming"?, Symon
    - Re: what is the difference between "configuring" and "programming"?, austin
    - Re: what is the difference between "configuring" and "programming"?, echoisme
    - Re: what is the difference between "configuring" and "programming"?, Symon
Send IP packets at the Ethernet level with VIRTEX4, pho
- Re: Send IP packets at the Ethernet level with VIRTEX4, Marc Randolph
- Re: Send IP packets at the Ethernet level with VIRTEX4, Nicholas Weaver
Software simulation of hardware evolution, apsolar
- Re: Software simulation of hardware evolution, Gabor
xilinx or digilent, CMOS
- Re: xilinx or digilent, GPE
  - Re: xilinx or digilent, CMOS
    - Re: xilinx or digilent, GPE
    - Re: xilinx or digilent, CMOS
    - Re: xilinx or digilent, Hal Murray
    - Re: xilinx or digilent, GPE
    - Re: xilinx or digilent, CMOS
    - Re: xilinx or digilent, CMOS
    - Re: xilinx or digilent, m_itoko
- Re: xilinx or digilent, Mike Harrison
Re: Verilog examples???, Jerry
802.11 IP, Jerry
Xilinx Xapp482: syncword?, Marco
10 Gigabit Ethernet FPGA boards..., Nicholas Weaver
- Re: 10 Gigabit Ethernet FPGA boards..., John Adair
chipscope problems, geoffrey wall
- Re: chipscope problems, Duane Clark
  - Re: chipscope problems, Johan Bernspång
  - Re: chipscope problems, geoffrey wall
- Re: chipscope problems, Zara
FPGA Development Board Wish List, John Adair
- Re: FPGA Development Board Wish List, John_H
  - Re: FPGA Development Board Wish List, John Adair
    - Re: FPGA Development Board Wish List, John_H
    - Re: FPGA Development Board Wish List, Sylvain Munaut
- Re: FPGA Development Board Wish List, Sylvain Munaut
  - Re: FPGA Development Board Wish List, John Adair
- Re: FPGA Development Board Wish List, Mike Harrison
  - Re: FPGA Development Board Wish List, John Adair
  - Re: FPGA Development Board Wish List, Sylvain Munaut
    - Re: FPGA Development Board Wish List, Mike Harrison
    - Re: FPGA Development Board Wish List, Sylvain Munaut
    - Re: FPGA Development Board Wish List, yusufilker
    - Re: FPGA Development Board Wish List, Simon
    - Re: FPGA Development Board Wish List, John Adair
- Re: FPGA Development Board Wish List, c d saunter
  - Re: FPGA Development Board Wish List, John Adair
    - Re: FPGA Development Board Wish List, Simon Peacock
    - Re: FPGA Development Board Wish List, John Adair
    - Re: FPGA Development Board Wish List, Simon Peacock
  - Re: FPGA Development Board Wish List, A. P. Richelieu
    - Re: FPGA Development Board Wish List, Mike Harrison
re:Good SystemC tutorials or books?, Dimitri Turbiner
Using bootloader, Marco
- Re: Using bootloader, Marco
Xilinx place and route cost table, huangjielg@xxxxxxxxx
- Re: Xilinx place and route cost table, John Adair
  - Re: Xilinx place and route cost table, Jeff Cunningham
- Re: Xilinx place and route cost table, John Retta
- <Possible follow-ups>
- Xilinx place and route cost table, huangjie
Stdin / stdout through RS232, Marco
- Re: Stdin / stdout through RS232, Sean Durkin
  - Re: Stdin / stdout through RS232, Marco
    - Re: Stdin / stdout through RS232, Benjamin Todd
    - Message not available
    - Message not available
    - Message not available
    - Re: Stdin / stdout through RS232, Joel Kolstad
    - Re: Stdin / stdout through RS232, wv9557
    - Re: Stdin / stdout through RS232, Thomas Entner
    - Re: Stdin / stdout through RS232, Philip Freidin
    - Re: Stdin / stdout through RS232, Marco
    - Re: Stdin / stdout through RS232, Philip Freidin
    - Re: Stdin / stdout through RS232, Marco
DCM does not do anything?, zoinks@xxxxxxxxxxxxxxx
- Re: DCM does not do anything?, Benjamin Todd
  - Re: DCM does not do anything?, zoinks@xxxxxxxxxxxxxxx
    - Re: DCM does not do anything?, Andrew FPGA
    - Re: DCM does not do anything?, zoinks@xxxxxxxxxxxxxxx
    - Re: DCM does not do anything?, zoinks@xxxxxxxxxxxxxxx
- Re: DCM does not do anything?, Duane Clark
  - Re: DCM does not do anything?, Richard Carey
Unused pins from FPGA to LAN91C111 (through NIOS), vizziee
digilent boards, CMOS
- <Possible follow-ups>
- digilent boards, CMOS
Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices), Alex
- Re: Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices), Mike Treseler
  - Re: Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices), Alex
uDMA Hard drive interface - putting together multiple programs., Terradestroyer
- Re: uDMA Hard drive interface - putting together multiple programs., Mark McDougall
  - Re: uDMA Hard drive interface - putting together multiple programs., Terradestroyer
    - Re: uDMA Hard drive interface - putting together multiple programs., Mike Treseler
    - Re: uDMA Hard drive interface - putting together multiple programs., Terradestroyer
Generic Memory-Mapped VHDL Module, James Morrison
- Re: Generic Memory-Mapped VHDL Module, Mike Treseler
- Re: Generic Memory-Mapped VHDL Module, MikeJ
Problem in using Hard Macros in Xilinx ISE 7.1, Love Singhal
How can I see the waveform of my verilog codes?, mikelinyoho
- Re: How can I see the waveform of my verilog codes?, Andy Peters
chipscope pro 6.3i clocking issue, wolf359mmcb
- Re: chipscope pro 6.3i clocking issue, Johan Bernspång
Problem in timing simulation(Altera), praveen . kantharajapura
- Re: Problem in timing simulation(Altera), Mike Treseler
ISE7.1i SP3, Dual port block ram, coregen issue, alpha
- Re: ISE7.1i SP3, Dual port block ram, coregen issue, Marko
  - Re: ISE7.1i SP3, Dual port block ram, coregen issue, alpha
Spartan slave-parallel development board, jvdh
Symmetric clocks with ALTERA Quartus, Ulrich Bangert
- Re: Symmetric clocks with ALTERA Quartus, Hal Murray
  - Re: Symmetric clocks with ALTERA Quartus, Ulrich Bangert
Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;, Tommy Thorn
- Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;, Neo
- Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;, Subroto Datta
real constants in XST, gallen
- Re: real constants in XST, Neo
  - Re: real constants in XST, gallen
Sharing SDRAM on Stratix II DSP Development kit, bjskill
Using very large number in VHDL, Nick
- Re: Using very large number in VHDL, Marc Randolph
  - Re: Using very large number in VHDL, Nick
    - Re: Using very large number in VHDL, MM
    - Re: Using very large number in VHDL, Marc Randolph
    - Re: Using very large number in VHDL, Nick
- Re: Using very large number in VHDL, Mike Treseler
Altera mysupport, jedi
- Re: Altera mysupport, Thomas Entner
Why some firmware is made by lattice's FPGA instead of C language?, mikelinyoho
- Re: Why some firmware is made by lattice's FPGA instead of C language?, Philip Freidin
Verilog translation, Marco
- Re: Verilog translation, Neo
  - Re: Verilog translation, Marco
What is the diffrences between lattice's FPGA and Xilinx's FPGA, mikelinyoho
- Re: What is the diffrences between lattice's FPGA and Xilinx's FPGA, Philip Freidin
- Re: What is the diffrences between lattice's FPGA and Xilinx's FPGA, Davy
  - Re: What is the diffrences between lattice's FPGA and Xilinx's FPGA, Gabor
Could you tell me some other good forums or website related?, rayjune
- Re: Could you tell me some other good forums or website related?, gallen
- Re: Could you tell me some other good forums or website related?, gallen
Kingston module structure, jms019
- Re: Kingston module structure, Jeremy Stringer
- Re: Kingston module structure, Duane Clark
USB Blaster, Jo Schambach
- Re: USB Blaster, Kolja Sulimma
Best FPGA for floating point performance, Marc Battyani
- Re: Best FPGA for floating point performance, Austin Lesea
  - Re: Best FPGA for floating point performance, Marc Battyani
  - Re: Best FPGA for floating point performance, Ray Andraka
- Re: Best FPGA for floating point performance, c d saunter
  - Re: Best FPGA for floating point performance, Marc Battyani
    - Re: Best FPGA for floating point performance, Thomas Womack
- Re: Best FPGA for floating point performance, JJ
  - Re: Best FPGA for floating point performance, Austin Lesea
    - Re: Best FPGA for floating point performance, JJ
    - Re: Best FPGA for floating point performance, Austin Lesea
    - Re: Best FPGA for floating point performance, JJ
    - Re: Best FPGA for floating point performance, Marc Battyani
    - Re: Best FPGA for floating point performance, Thomas Womack
    - Re: Best FPGA for floating point performance, austin
    - Re: Best FPGA for floating point performance, robin.bruce@xxxxxxxxx
    - Re: Best FPGA for floating point performance, gantlord
    - Re: Best FPGA for floating point performance, austin
    - Re: Best FPGA for floating point performance, Simon Peacock
    - Re: Best FPGA for floating point performance, JJ
    - Re: Best FPGA for floating point performance, mk
    - Re: Best FPGA for floating point performance, JJ
    - Re: Best FPGA for floating point performance, mk
    - Re: Best FPGA for floating point performance, Tommy Thorn
    - Re: Best FPGA for floating point performance, Simon Peacock
    - Re: Best FPGA for floating point performance, JJ
    - Re: Best FPGA for floating point performance, Simon Peacock
    - Re: Best FPGA for floating point performance, JJ
    - Re: Best FPGA for floating point performance, Jim Granville
    - Re: Best FPGA for floating point performance, JJ
    - Re: Best FPGA for floating point performance, JJ
  - Re: Best FPGA for floating point performance, Marc Battyani
- Re: Best FPGA for floating point performance, glen herrmannsfeldt
  - Re: Best FPGA for floating point performance, Marc Battyani
PLL, Designfreek
- Re: PLL, Subroto Datta
- Re: PLL, Ben Twijnstra
looking for OLD OLD software, Chris Beg
- Re: looking for OLD OLD software, Austin Lesea
JOB: Sr. Hardware Design Engineer- FPGA/ASIC - PCB Design- Austin, TX, Dee Dee Dial, Executive Technology Recruiter
Download bit stream onto ml310 ( virtex 2 pro ) using uart cable, Nitesh
- Re: Download bit stream onto ml310 ( virtex 2 pro ) using uart cable, Paul Hartke
  - Re: Download bit stream onto ml310 ( virtex 2 pro ) using uart cable, Nitesh
DDR memory writing all data twice & IPIF questions, zoinks@xxxxxxxxxxxxxxx
XST Help - Device Utilization Woes, Brandon
- Re: XST Help - Device Utilization Woes, Symon
- Re: XST Help - Device Utilization Woes, Vladislav Muravin
- Re: XST Help - Device Utilization Woes, Simon Peacock
  - Re: XST Help - Device Utilization Woes, Brandon
    - Re: XST Help - Device Utilization Woes, John McCaskill
    - Re: XST Help - Device Utilization Woes, Andrew FPGA
    - Re: XST Help - Device Utilization Woes, Brandon
    - Re: XST Help - Device Utilization Woes, Andrew FPGA
- Re: XST Help - Device Utilization Woes, aholtzma
Two microblaze in EDK, mvetromille
- Re: Two microblaze in EDK, Paul Hartke
- Re: Two microblaze in EDK, Adrian Knoth
  - Re: Two microblaze in EDK, Paul Hartke
    - Re: Two microblaze in EDK, Adrian Knoth
    - Re: Two microblaze in EDK, Paul Hartke
    - Re: Two microblaze in EDK, Adrian Knoth
State Machine and BUFG, Marco
- Re: State Machine and BUFG, Sean Durkin
- Re: State Machine and BUFG, Marco
  - Re: State Machine and BUFG, Kolja Sulimma
    - Re: State Machine and BUFG, Marco
    - Re: State Machine and BUFG, Andy Peters
    - Re: State Machine and BUFG, Marco
- Re: State Machine and BUFG, Vladislav Muravin
[Q] Synthesis : HowTo Preserve FSM encodings, Markus Meng
- Re: Synthesis : HowTo Preserve FSM encodings, Neo
  - Re: Synthesis : HowTo Preserve FSM encodings, Alex
- Re: Synthesis : HowTo Preserve FSM encodings, des00
Re: Fastest way to compute floating point log and exp, Eric Smith
Problem with quartus 5.0 sp1, czerstwy
- Re: Problem with quartus 5.0 sp1, Subroto Datta
  - Re: Problem with quartus 5.0 sp1, czerstwy
- Re: Problem with quartus 5.0 sp1, Sylvain Munaut
Modelsim on a remote display, Marco
- Re: Modelsim on a remote display, unfrostedpoptart
  - Re: Modelsim on a remote display, Marco
    - Re: Modelsim on a remote display, Sylvain Munaut
    - Re: Modelsim on a remote display, Marco
    - Re: Modelsim on a remote display, Jon Beniston
    - Re: Modelsim on a remote display, Marco
    - Re: Modelsim on a remote display, Mike Treseler
Xilinx ISE on remtoe Display, Andrew Greensted
- Re: Xilinx ISE on remtoe Display, Andrew Greensted
  - Re: Xilinx ISE on remtoe Display, Sean Durkin
- Re: Xilinx ISE on remtoe Display, Hiding in Plain Sight
  - Re: Xilinx ISE on remtoe Display, Andrew Greensted
- Re: Xilinx ISE on remtoe Display, Adrian Knoth
- Re: Xilinx ISE on remtoe Display, Jim Wu
  - Re: Xilinx ISE on remtoe Display, Andrew Greensted
- Re: Xilinx ISE on remtoe Display, Andrew Greensted
Chipscope pro : timing constraint?, Pasacco
- Re: Chipscope pro : timing constraint?, Ed McGettigan
  - Re: Chipscope pro : timing constraint?, Pasacco
    - Re: Chipscope pro : timing constraint?, Ed McGettigan
    - Re: Chipscope pro : timing constraint?, Pasacco
    - Re: Chipscope pro : timing constraint?, Ed McGettigan
    - Re: Chipscope pro : timing constraint?, Andy Peters
    - Re: Chipscope pro : timing constraint?, Pasacco
    - Re: Chipscope pro : timing constraint?, Ed McGettigan
    - Re: Chipscope pro : timing constraint?, Pasacco
Easy USB2.0 hi-speed device solutions ?, Mike Harrison
- Re: Easy USB2.0 hi-speed device solutions ?, Alex
- Re: Easy USB2.0 hi-speed device solutions ?, Manfred Kraus
- Re: Easy USB2.0 hi-speed device solutions ?, Gregory C. Read
FPGA-Based system design project, easystep2
- Re: FPGA-Based system design project, Eric
  - Re: FPGA-Based system design project, Javier Castillo
- Re: FPGA-Based system design project, Vladislav Muravin
Changing data into mapped register, Marco
Evolutionary VHDL code example, apsolar
- Re: Evolutionary VHDL code example, Neo
- Re: Evolutionary VHDL code example, Eric
  - Re: Evolutionary VHDL code example, Eric
- Re: Evolutionary VHDL code example, Andrew Greensted
  - Re: Evolutionary VHDL code example, apsolar
- Re: Evolutionary VHDL code example, Phil Tomson
Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription, Albert Chang
Antti's last comp.arch.fpga posting, Antti Lukats
- Re: Antti's last comp.arch.fpga posting, zcsizmadia
- Re: Antti's last comp.arch.fpga posting, Jim Granville
- Re: Antti's last comp.arch.fpga posting, oen_no_spam
- Re: Antti's last comp.arch.fpga posting, Vladislav Muravin
  - Re: Antti's last comp.arch.fpga posting, Pete Fraser
    - Re: Antti's last comp.arch.fpga posting, Vladislav Muravin
  - Re: Antti's last comp.arch.fpga posting, Austin Lesea
    - Message not available
    - Re: Antti's last comp.arch.fpga posting, austin
Altera NIOSII IDE problem???, Monica
- Re: Altera NIOSII IDE problem???, GMM50
- Re: Altera NIOSII IDE problem???, Nial Stewart
  - Re: Altera NIOSII IDE problem???, ALuPin
image sensor, Bob
- Re: image sensor, Gabor
- Re: image sensor, james
  - image sensor, Bob
    - Re: image sensor, Mike Treseler
- Re: image sensor, Jerome
GSPx 2005 Conference, Sudhir . Singh
XC5200 tool help needed, Paul Urbanus
- Re: XC5200 tool help needed, Gabor
- Re: XC5200 tool help needed, Austin Lesea
- Re: XC5200 tool help needed, Jing
Re: Virtex-2 Pro: Configuration Frames, John Williams
Clock generation, alessandro . strazzero
- Re: Clock generation, Alex
- Re: Clock generation, Vladislav Muravin
- Re: Clock generation, Austin Lesea
- Re: Clock generation, Philip Freidin
AHDL Abandoned in Quartus?, jjlindula@xxxxxxxxxxx
- Re: AHDL Abandoned in Quartus?, Subroto Datta
  - Re: AHDL Abandoned in Quartus?, Jim Granville
    - Re: AHDL Abandoned in Quartus?, Kolja Sulimma
- Re: AHDL Abandoned in Quartus?, htoerrin
Re: Creating EDIF from VHDL, Andy Peters
- <Possible follow-ups>
- Re: Creating EDIF from VHDL, Jeremy Stringer
  - Re: Creating EDIF from VHDL, Duane Clark
18-bit ROM in verilog, Brian Dam Pedersen
- Re: 18-bit ROM in verilog, Vladislav Muravin
  - Re: 18-bit ROM in verilog, Brian Dam Pedersen
How to disconnect a signal?, Marco
- Re: How to disconnect a signal?, Hubble
  - Re: How to disconnect a signal?, Marco
Spartan-3 configuration -- peculiar problem, ScreamingFPGA
- Re: Spartan-3 configuration -- peculiar problem, John Larkin
  - Re: Spartan-3 configuration -- peculiar problem, ScreamingFPGA
    - Re: Spartan-3 configuration -- peculiar problem, John Larkin
    - Re: Spartan-3 configuration -- peculiar problem, ScreamingFPGA
    - Re: Spartan-3 configuration -- peculiar problem, John Larkin
    - Re: Spartan-3 configuration -- peculiar problem, Andrew FPGA
    - Re: Spartan-3 configuration -- peculiar problem, ScreamingFPGA
    - Re: Spartan-3 configuration -- peculiar problem, John Larkin
    - Re: Spartan-3 configuration -- peculiar problem, Peter Alfke
    - Re: Spartan-3 configuration -- peculiar problem, John Larkin
    - Re: Spartan-3 configuration -- peculiar problem, Peter Alfke
    - Re: Spartan-3 configuration -- peculiar problem, John Larkin
    - Re: Spartan-3 configuration -- peculiar problem, Hal Murray
- Re: Spartan-3 configuration -- peculiar problem, Stephan
- Re: Spartan-3 configuration -- peculiar problem, ScreamingFPGA
  - Re: Spartan-3 configuration -- peculiar problem, John Larkin
    - Re: Spartan-3 configuration -- peculiar problem, ScreamingFPGA
    - Re: Spartan-3 configuration -- peculiar problem, Symon
    - Re: Spartan-3 configuration -- peculiar problem, John Larkin
VHDL Array indexing Issue in Modelsim, pinod01
- Re: VHDL Array indexing Issue in Modelsim, ALuPin
- Re: VHDL Array indexing Issue in Modelsim, Andy Peters
- Re: VHDL Array indexing Issue in Modelsim, Hubble
  - Re: VHDL Array indexing Issue in Modelsim, pinod01
Re: globally asyncronous vs locally syncronous?, Alex
- Re: globally asyncronous vs locally syncronous?, ernie
Delay implementation and logic optimization., Alex
- Re: Delay implementation and logic optimization., Andy Peters
  - Re: Delay implementation and logic optimization., Alex
    - Re: Delay implementation and logic optimization., Austin Lesea
    - Re: Delay implementation and logic optimization., Alex
XST (ISE 6.1i): Error: It's interesting and surprising, QRaheeL
- Re: XST (ISE 6.1i): Error: It's interesting and surprising, johnp
- Re: XST (ISE 6.1i): Error: It's interesting and surprising, Andy Peters
  - Re: XST (ISE 6.1i): Error: It's interesting and surprising, Symon
- Re: XST (ISE 6.1i): Error: It's interesting and surprising, Vladislav Muravin
Clock for serializer with a Spartan3, dalai lamah
- Re: Clock for serializer with a Spartan3, Marc Randolph
  - Re: Clock for serializer with a Spartan3, Antti Lukats
    - Re: Clock for serializer with a Spartan3, dalai lamah
    - Re: Clock for serializer with a Spartan3, dalai lamah
  - Re: Clock for serializer with a Spartan3, dalai lamah
Modular design flow, Fpga_Designer
- Re: Modular design flow, Andy Peters
  - Re: Modular design flow, Fpga_Designer
- Re: Modular design flow, Javier Castillo
Avnet spartan3E development board, CMOS
- Re: Avnet spartan3E development board, Antti Lukats
  - Re: Avnet spartan3E development board, rickystickyrick
- Re: Avnet spartan3E development board, Alf Katz
Glitches in Output of FSM, Sudhir . Singh
- Re: Glitches in Output of FSM, Peter Alfke
  - Re: Glitches in Output of FSM, Sudhir . Singh
Peter Alfke's SPDT Switch Debouncer, v_mirgorodsky
- Re: Peter Alfke's SPDT Switch Debouncer, Slurp
  - Re: Peter Alfke's SPDT Switch Debouncer, v_mirgorodsky
    - Re: Peter Alfke's SPDT Switch Debouncer, mk
    - Re: Peter Alfke's SPDT Switch Debouncer, v_mirgorodsky
    - Re: Peter Alfke's SPDT Switch Debouncer, Peter Alfke
    - Re: Peter Alfke's SPDT Switch Debouncer, Jim Granville
    - Re: Peter Alfke's SPDT Switch Debouncer, Austin Lesea
    - Re: Peter Alfke's SPDT Switch Debouncer, Peter Alfke
    - Re: Peter Alfke's SPDT Switch Debouncer, Jim Granville
    - Re: Peter Alfke's SPDT Switch Debouncer, Peter Alfke
    - Re: Peter Alfke's SPDT Switch Debouncer, Uwe Bonnes
    - Re: Peter Alfke's SPDT Switch Debouncer, Austin Lesea
    - Re: Peter Alfke's SPDT Switch Debouncer, Kolja Sulimma
    - Re: Peter Alfke's SPDT Switch Debouncer, Austin Lesea
- Re: Peter Alfke's SPDT Switch Debouncer, Symon
  - Re: Peter Alfke's SPDT Switch Debouncer, Antti Lukats
    - Re: Peter Alfke's SPDT Switch Debouncer, Uwe Bonnes
    - Re: Peter Alfke's SPDT Switch Debouncer, Antti Lukats
Troubles when mapping registers into microblaze address space, Marco
- Re: Troubles when mapping registers into microblaze address space, Marco
- Re: Troubles when mapping registers into microblaze address space, usenet
EDK IPIF + User Core, el_boricua
- Re: EDK IPIF + User Core, Paul Hartke
freeware/reasonable-ware c compiler for picoblaze, Dave
- Re: freeware/reasonable-ware c compiler for picoblaze, Andy Peters
  - Re: freeware/reasonable-ware c compiler for picoblaze, Dave
Atmel AT40k/94k Configuration Format Documentation, William Sealey Gosset
- Re: Atmel AT40k/94k Configuration Format Documentation, Antti Lukats
Xilinx ISE 6.3i on Gentoo Linux, Andrew Greensted
- Re: Xilinx ISE 6.3i on Gentoo Linux, Hiding in Plain Sight
  - Re: Xilinx ISE 6.3i on Gentoo Linux, Andrew Greensted
- re:Xilinx ISE 6.3i on Gentoo Linux, saned
- Re: Xilinx ISE 6.3i on Gentoo Linux, Andrew Greensted
Regarding clock muxing, praveen . kantharajapura
- Re: Regarding clock muxing, Gabor
- Re: Regarding clock muxing, Vladislav Muravin
- Re: Regarding clock muxing, Peter Alfke
high speed image capture, CMOS
- Re: high speed image capture, Antti Lukats
- Re: high speed image capture, ALuPin
- Re: high speed image capture, rudi
  - Re: high speed image capture, Thomas Entner
- Re: high speed image capture, Mike Harrison
  - Re: high speed image capture, Gabor
    - Re: high speed image capture, CMOS
    - Re: high speed image capture, Hal Murray
Microblaze, cspatel
creating HARD MACROs broken in ISE 7.1 SP3 ?, Antti Lukats
- Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, austin
  - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, Antti Lukats
  - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, Antti Lukats
    - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, austin
    - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, Antti Lukats
- Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, bret . wade
  - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, Antti Lukats
    - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, Hal Murray
    - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, Antti Lukats
    - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, bret . wade
    - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, Antti Lukats
    - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, Andy Peters
    - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, Bob Perlman
- Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, GPE
  - Re: creating HARD MACROs broken in ISE 7.1 SP3 ?, austin
    - ISE 7.1 'improvements' plus meandering...., GPE
    - Re: ISE 7.1 'improvements' plus meandering...., Jim Granville
    - Re: ISE 7.1 'improvements' plus meandering...., GPE
    - Re: ISE 7.1 'improvements' plus meandering...., Jim Granville
    - Re: ISE 7.1 'improvements' plus meandering...., GPE
    - Re: ISE 7.1 'improvements' plus meandering...., Jim Granville
use of memory in verilog(uegent please), ravindra kalla
[Q] Virtex-IV with RLDRAM-II any experience with it?, Markus Meng
Clocks, Stefan
- Re: Clocks, Vladislav Muravin
  - Re: Clocks, Stefan
    - Re: Clocks, Vladislav Muravin
- Re: Clocks, Rene Tschaggelar
LatticeXP availability, Maki
- Re: LatticeXP availability, Antti Lukats
XILINX POWERPC <-> Embedded tri-mode-MAC connection, francesco . poderico
- Re: XILINX POWERPC <-> Embedded tri-mode-MAC connection, Paul Hartke
rom, u_stadler@xxxxxxxx
- Re: rom, ALuPin
  - Re: rom, u_stadler@xxxxxxxx
- Re: rom, backhus
Delays in verilog, Gerr
- Re: Delays in verilog, allanherriman
- Re: Delays in verilog, johnp
- Re: Delays in verilog, Jonathan Bromley
  - Re: Delays in verilog, Tullio Grassi
    - Re: Delays in verilog, Jonathan Bromley
    - Re: Delays in verilog, Simon Peacock
- Re: Delays in verilog, Javier Castillo
Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, PeterC
- Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, Peter Alfke
  - Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, PeterC
    - Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, Peter Alfke
    - Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, PeterC
    - Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, Jim Granville
    - Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, Peter Alfke
    - Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, PeterC
    - Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, PeterC
    - Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, Ray Andraka
- Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, Jim Granville
  - Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?, PeterC
EDK and ISE questions, el_boricua
- Re: EDK and ISE questions, Paul Hartke
ASIC suggestions, dave94024
- Re: ASIC suggestions, francesco . poderico
  - Re: ASIC suggestions, Rob
- Re: ASIC suggestions, haitaoz
- Re: ASIC suggestions, dave94024
  - Re: ASIC suggestions, Austin Lesea
    - Re: ASIC suggestions, dave94024
    - Re: ASIC suggestions, dave94024
    - Re: ASIC suggestions, Antti Lukats
    - Re: ASIC suggestions, dave94024
Xilinx: Where has all the data gone?, Gabor
- Re: Xilinx: Where has all the data gone?, Gabor
XBERT module., sjm1218
- Re: XBERT module., austin
  - Re: XBERT module., sjm1218
Using an oscillator in a rugged environment, alessandro . strazzero
- Re: Using an oscillator in a rugged environment, Gabor
- Re: Using an oscillator in a rugged environment, Ben Twijnstra
- Re: Using an oscillator in a rugged environment, Peter Alfke
Cypress CY7B923/33 models, ernie
- Re: Cypress CY7B923/33 models, Klaus Falser
  - Re: Cypress CY7B923/33 models, ernie
    - Re: Cypress CY7B923/33 models, ernie
    - Re: Cypress CY7B923/33 models, Mike Treseler
    - Re: Cypress CY7B923/33 models, ernie
Xilinx Forge compiler is discontinued ??, Antti Lukats
- Re: Xilinx Forge compiler is discontinued ??, Antti Lukats
FPGA Programming using Block Design Files or Graphic Design Files, jjlindula@xxxxxxxxxxx
- Re: FPGA Programming using Block Design Files or Graphic Design Files, Monica
  - Re: FPGA Programming using Block Design Files or Graphic Design Files, Mike Treseler
- Re: FPGA Programming using Block Design Files or Graphic Design Files, Andy Peters
  - Re: FPGA Programming using Block Design Files or Graphic Design Files, jjlindula@xxxxxxxxxxx
- Re: FPGA Programming using Block Design Files or Graphic Design Files, jjlindula@xxxxxxxxxxx
  - Re: FPGA Programming using Block Design Files or Graphic Design Files, Andy Peters
- Re: FPGA Programming using Block Design Files or Graphic Des, fahadislam2002
Rapid prototyping in FPGA, sarath
- Re: Rapid prototyping in FPGA, backhus
  - Re: Rapid prototyping in FPGA, sarath
- <Possible follow-ups>
- Rapid prototyping in FPGA, sarath
How to setup Analyzer in ChipScope Pro, Pasacco
- Re: How to setup Analyzer in ChipScope Pro, patrick . melet
  - Re: How to setup Analyzer in ChipScope Pro, Pasacco
  - Re: How to setup Analyzer in ChipScope Pro, Andy Peters
Welcome back Mr. Knapp, oen_no_spam
- Re: Welcome back Mr. Knapp, Antti Lukats
  - Re: Welcome back Mr. Knapp, Thomas Entner
- Re: Welcome back Mr. Knapp, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
  - Re: Welcome back Mr. Knapp, Antti Lukats
    - Re: Welcome back Mr. Knapp, Thomas Entner
    - Re: Welcome back Mr. Knapp, Antti Lukats
    - Re: Welcome back Mr. Knapp, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
Fast Recompilation of an XPS project, Suhrid
- Re: Fast Recompilation of an XPS project, edvenson
  - Re: Fast Recompilation of an XPS project, Suhrid
MPEG-2 links please, Monica
- Re: MPEG-2 links please, Georg Acher
  - Re: MPEG-2 links please, Monica
    - Re: MPEG-2 links please, Luis Vaccaro
Linux driver for Embedded TEMAC in Virtex4, Fridolin
- Re: Linux driver for Embedded TEMAC in Virtex4, Paul Hartke
  - Re: Linux driver for Embedded TEMAC in Virtex4, Fridolin
partial reconfig with multipiers, Christoph Lauer
What are IO standard defaults in S3 ?, Mike Harrison
- Re: What are IO standard defaults in S3 ?, Symon
- Re: What are IO standard defaults in S3 ?, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
START /STOP sync pattern, praveen . kantharajapura
- Re: START /STOP sync pattern, Kryten
- Re: START /STOP sync pattern, backhus
- Re: START /STOP sync pattern, Ico
Incorporating Cores to the Virtex2Pro PLB, el_boricua
- Re: Incorporating Cores to the Virtex2Pro PLB, Paul Hartke
  - Re: Incorporating Cores to the Virtex2Pro PLB, el_boricua
    - Re: Incorporating Cores to the Virtex2Pro PLB, Paul Hartke
No submodule instantiation as seen in FPGA Editor, John D. Davis
- Re: No submodule instantiation as seen in FPGA Editor, John D. Davis
Can use SRAM instead of VRAM ......... how ???????????, fahadislam2002
- Re: Can use SRAM instead of VRAM ......... how ???????????, Andy Peters
can use bram for VGA, fahadislam2002
- Re: can use bram for VGA, Antti Lukats
- Re: can use bram for VGA, Peter Alfke
  - Re: can use bram for VGA, Paul Marciano
- Re: can use bram for VGA, fahadislam2002
  - Re: can use bram for VGA, Andy Peters
- Re: can use bram for VGA, fahadislam2002
- Re: can use bram for VGA, fahadislam2002
  - Re: can use bram for VGA, Andreas Ehliar
how to reduce vga memory????????, fahadislam2002
- Re: how to reduce vga memory????????, Mark McDougall
  - Re: how to reduce vga memory????????, Mark McDougall
- Re: how to reduce vga memory????????, fahadislam2002
  - Re: how to reduce vga memory????????, Mark McDougall
    - Re: how to reduce vga memory????????, james
    - Re: how to reduce vga memory????????, Mark McDougall
    - Re: how to reduce vga memory????????, james
- Re: how to reduce vga memory????????, Paul Marciano
  - Re: how to reduce vga memory????????, Paul Marciano
    - Re: how to reduce vga memory????????, Paul Marciano
Re: Creating Variable Delay for output signals in an XCV1000, John D. Davis
Re: virtex 4 : how can I know the clock region coverage?, google_comp.arch.fpga@xxxxxxxxxxxx
warning for ODDR primitive?, Tim Verstraete
- Re: warning for ODDR primitive?, Luc
ZLIB anyone?, irish
sequence detection using shift register approach, praveen . kantharajapura
- Re: sequence detection using shift register approach, Gabor
  - Re: sequence detection using shift register approach, praveen . kantharajapura
    - Re: sequence detection using shift register approach, usenet_10
    - Re: sequence detection using shift register approach, Symon
Hiding data inside a FPGA, Javier Castillo
- Re: Hiding data inside a FPGA, Gabor
  - Re: Hiding data inside a FPGA, Mike Harrison
- Re: Hiding data inside a FPGA, Sylvain Munaut
- Re: Hiding data inside a FPGA, usenet_10
- Re: Hiding data inside a FPGA, jholley
  - Re: Hiding data inside a FPGA, ALuPin
    - Re: Hiding data inside a FPGA, Antti Lukats
  - Re: Hiding data inside a FPGA, Javier Castillo
    - Re: Hiding data inside a FPGA, Antti Lukats
    - Re: Hiding data inside a FPGA, Andy Peters
- Re: Hiding data inside a FPGA, Kris Vorwerk
ModelSim Error, u_stadler@xxxxxxxx
- Re: ModelSim Error, anil
Active module phase with multiple module instances, Christoph Lauer
Spartan-3: Own P&R, generate bitstream from, Tobias Weihmann
- Re: Spartan-3: Own P&R, generate bitstream from, Antti Lukats
- Re: Spartan-3: Own P&R, generate bitstream from, Philip Freidin
  - Re: Spartan-3: Own P&R, generate bitstream from, Tobias Weihmann
    - Re: Spartan-3: Own P&R, generate bitstream from, Philip Freidin
    - Re: Spartan-3: Own P&R, generate bitstream from, Tobias Weihmann
    - Re: Spartan-3: Own P&R, generate bitstream from, Antti Lukats
circular buffer(its urgent), ravindra kalla
- Re: circular buffer(its urgent), Sylvain Munaut
if you or your friend have design experience about USB2.0 OTG and 10G Ethernet,plz contact us:, fopisarr
- Re: if you or your friend have design experience about USB2.0 OTG and 10G Ethernet,plz contact us:, fopisarr
power of two multiplier, mk
NIOS Small C library, Pratip Mukherjee
- Re: NIOS Small C library, Heinz-Jürgen Oertel
test, pepe70
Xilinx V4 & DDR2 Memory Interface, Enzo Guerra
- Re: Xilinx V4 & DDR2 Memory Interface, austin
- Re: Xilinx V4 & DDR2 Memory Interface, Bob Perlman
Re: Free 8 bit micro for fpga, dave
How to properly use Analyzer, ILA ChipScopePro, pasacco
Xilinx XC4VFX140 Availability ?, Tullio Grassi
- Re: Xilinx XC4VFX140 Availability ?, austin
Virtex 4 development boards, geoffrey wall
Holding in output registers, ALuPin
- Re: Holding in output registers, Andy Peters
  - Re: Holding in output registers, ALuPin
    - Re: Holding in output registers, Nicolas Matringe
    - Re: Holding in output registers, ALuPin
    - Re: Holding in output registers, Subroto Datta
    - Re: Holding in output registers, ALuPin
    - Re: Holding in output registers, ALuPin
- <Possible follow-ups>
- Holding in output registers, ALuPin
about the Hold signal of serial flash ., kelvins
- Re: about the Hold signal of serial flash ., Antti Lukats
Re: Spartan-3 configuring problem, pkkeng88
Re: System Engineering in the R/D World, Jeremy Stringer
- Re: System Engineering in the R/D World, Adrian Spilca
xilinx nallatech v4 extreme dsp development boards, geoffrey wall
- Re: xilinx nallatech v4 extreme dsp development boards, Roel
Xilinx Impact order, Brad Smallridge
- Re: Xilinx Impact order, austin
  - Re: Xilinx Impact order, Sean Durkin
    - Re: Xilinx Impact order, Benjamin Todd
    - Re: Xilinx Impact order, c d saunter
    - Re: Xilinx Impact order, Sean Durkin
  - Re: Xilinx Impact order, Brad Smallridge
Anyone had this error / knows what it means?, simon.stockton@xxxxxxxxxxxxxx
Auto generation of memory files, Paul Solomon
- Re: Auto generation of memory files, Paul Solomon
- Re: Auto generation of memory files, Jonathan Bromley
  - Re: Auto generation of memory files, Paul Solomon
    - Re: Auto generation of memory files, Jonathan Bromley
    - Re: Auto generation of memory files, Paul Solomon
    - Re: Auto generation of memory files, Jonathan Bromley
    - Re: Auto generation of memory files, Paul Solomon
Where can i find GeneticFPGA toolkit, apsolar
- Re: Where can i find GeneticFPGA toolkit, Antti Lukats
- Re: Where can i find GeneticFPGA toolkit, Peter Alfke
  - Re: Where can i find GeneticFPGA toolkit, apsolar
    - Re: Where can i find GeneticFPGA toolkit, Peter Alfke
    - Re: Where can i find GeneticFPGA toolkit, Eric
    - Re: Where can i find GeneticFPGA toolkit, Peter Alfke
    - Re: Where can i find GeneticFPGA toolkit, apsolar
    - Re: Where can i find GeneticFPGA toolkit, Eric
    - Re: Where can i find GeneticFPGA toolkit, Rob Ryland
    - Re: Where can i find GeneticFPGA toolkit, apsolar
    - Re: Where can i find GeneticFPGA toolkit, Eric
    - Re: Where can i find GeneticFPGA toolkit, apsolar
    - Re: Where can i find GeneticFPGA toolkit, Eric
    - Re: Where can i find GeneticFPGA toolkit, apsolar
    - Re: Where can i find GeneticFPGA toolkit, Eric
    - Re: Where can i find GeneticFPGA toolkit, Eric
    - Re: Where can i find GeneticFPGA toolkit, apsolar
    - Re: Where can i find GeneticFPGA toolkit, Eric
    - Re: Where can i find GeneticFPGA toolkit, Eric
Quartus II 4.2 Incremental Systhesis, Paul Solomon
- Re: Quartus II 4.2 Incremental Systhesis, Ben Twijnstra
  - Re: Quartus II 4.2 Incremental Systhesis, Subroto Datta
3.3V tolerant configuration interface Spartan 3, Yaju Nagaonkar
- Re: 3.3V tolerant configuration interface Spartan 3, Yaju Nagaonkar
Modulation Clock to set FPGA timing, cyd
- Re: Modulation Clock to set FPGA timing, Andrew FPGA
  - Re: Modulation Clock to set FPGA timing, cyd
- Re: Modulation Clock to set FPGA timing, Peter Alfke
- Re: Modulation Clock to set FPGA timing, Vladislav Muravin
  - Re: Modulation Clock to set FPGA timing, cyd
Legality of type conversion on instance ports?, Brandon
- Re: Legality of type conversion on instance ports?, Jonathan Bromley
  - Re: Legality of type conversion on instance ports?, Brandon
    - Re: Legality of type conversion on instance ports?, Jonathan Bromley
    - Re: Legality of type conversion on instance ports?, Brandon
How to import EDIF netlist into ISE webpack 7.1, Monica
- Re: How to import EDIF netlist into ISE webpack 7.1, Sean Durkin
  - Re: How to import EDIF netlist into ISE webpack 7.1, Monica
  - Re: How to import EDIF netlist into ISE webpack 7.1, Brian Dam Pedersen
    - Re: How to import EDIF netlist into ISE webpack 7.1, Sean Durkin
RocketIO connexion to an optical transceiver, jfh
- Re: RocketIO connexion to an optical transceiver, jfh
  - Re: RocketIO connexion to an optical transceiver, Symon
    - Re: RocketIO connexion to an optical transceiver, jfh
  - Re: RocketIO connexion to an optical transceiver, Marc Randolph
    - Re: RocketIO connexion to an optical transceiver, jfh
    - Re: RocketIO connexion to an optical transceiver, Symon
    - Re: RocketIO connexion to an optical transceiver, Symon
    - Re: RocketIO connexion to an optical transceiver, Marc Randolph
    - Re: RocketIO connexion to an optical transceiver, Martin Thompson
    - Re: RocketIO connexion to an optical transceiver, Marc Randolph
    - Re: RocketIO connexion to an optical transceiver, Symon
    - Re: RocketIO connexion to an optical transceiver, Sean Durkin
    - Re: RocketIO connexion to an optical transceiver, Symon
Area Group IOB Range, praetorian
- Re: Area Group IOB Range, bret . wade
  - Re: Area Group IOB Range, praetorian
Re: Virtex-4 hot-swappable?, JD_Design
- Re: Virtex-4 hot-swappable?, JD_Design
- Re: Virtex-4 hot-swappable?, austin
5V non-volatile reprogrammable FPGA/CPLD, Maaf
- Re: 5V non-volatile reprogrammable FPGA/CPLD, Mike Harrison
  - Re: 5V non-volatile reprogrammable FPGA/CPLD, Maaf
- Re: 5V non-volatile reprogrammable FPGA/CPLD, Jim Granville
  - Re: 5V non-volatile reprogrammable FPGA/CPLD, Karl
Programmable frequency synthesizer with Xilinx DCM, dalai lamah
- Re: Programmable frequency synthesizer with Xilinx DCM, Peter Alfke
  - Re: Programmable frequency synthesizer with Xilinx DCM, Ben Twijnstra
    - Re: Programmable frequency synthesizer with Xilinx DCM, Peter Alfke
    - Re: Programmable frequency synthesizer with Xilinx DCM, johnp
    - Re: Programmable frequency synthesizer with Xilinx DCM, Ben Twijnstra
    - Re: Programmable frequency synthesizer with Xilinx DCM, Peter Alfke
    - Re: Programmable frequency synthesizer with Xilinx DCM, Jim Granville
    - Re: Programmable frequency synthesizer with Xilinx DCM, bobrics
    - Re: Programmable frequency synthesizer with Xilinx DCM, Peter Alfke
    - Re: Programmable frequency synthesizer with Xilinx DCM, Ben Twijnstra
    - Re: Programmable frequency synthesizer with Xilinx DCM, Peter Alfke
    - Re: Programmable frequency synthesizer with Xilinx DCM, Jim Granville
    - Re: Programmable frequency synthesizer with Xilinx DCM, Peter Alfke
  - Re: Programmable frequency synthesizer with Xilinx DCM, Jim Granville
    - Re: Programmable frequency synthesizer with Xilinx DCM, Peter Alfke
    - Re: Programmable frequency synthesizer with Xilinx DCM, Jim Granville
- Re: Programmable frequency synthesizer with Xilinx DCM, austin
ML401 JTAG configuration problem, Pete Fraser
- Re: ML401 JTAG configuration problem, Nenad
  - Re: ML401 JTAG configuration problem, Pete Fraser
    - Re: ML401 JTAG configuration problem, Nenad
Porting Actel code, Baxter
- Re: Porting Actel code, Mike Treseler
  - Re: Porting Actel code, Baxter
    - Re: Porting Actel code, Antti Lukats
- Re: Porting Actel code, usenet_10
  - Re: Porting Actel code, Baxter
    - Re: Porting Actel code, Mike Treseler
    - Re: Porting Actel code, Neill A
Xilinx libraries missing,j83a/c modulator IP core, Monica
How to manage user 'reset' for post-synthesis simulation, pasacco
- Re: How to manage user 'reset' for post-synthesis simulation, Gladiator
Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript, Amir Tabatabaei
- Re: Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript, Brian Dam Pedersen
  - Re: Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript, Amir Tabatabaei
    - Re: Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript, Brian Dam Pedersen
    - Re: Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript, Sietse Achterop
    - Re: Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript, Piotr Wiszowaty
Re: Sparan S3E availability update, oen_no_spam
- Re: Sparan S3E availability update, Antti Lukats
  - Re: Sparan S3E availability update, oen_no_spam
    - Re: Sparan S3E availability update, Antti Lukats
    - Re: Sparan S3E availability update, Peter Alfke
    - Re: Sparan S3E availability update, oen_no_spam
lut problem, mike
fpga- DDR or DDR2, nahum_barnea
- Re: fpga- DDR or DDR2, ALuPin
- Re: fpga- DDR or DDR2, Sean Durkin
  - Re: fpga- DDR or DDR2, Jeremy Stringer
    - Re: fpga- DDR or DDR2, Paul Hartke
AVNET Xilinx Spartan3 board, example problem, Monica
- Re: AVNET Xilinx Spartan3 board, example problem, Antti Lukats
  - Re: AVNET Xilinx Spartan3 board, example problem, Monica
Re: Asynchronous Priority comparator, backhus
- Re: Asynchronous Priority comparator, Andrew FPGA
  - Re: Asynchronous Priority comparator, llabakdas
Conversion of Schematic to Verilog/VHDL, morpheus
- Re: Conversion of Schematic to Verilog/VHDL, backhus
- Re: Conversion of Schematic to Verilog/VHDL, ALuPin
- Re: Conversion of Schematic to Verilog/VHDL, Vladislav Muravin
Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Ray Andraka
Re: Distributed Arithmetic Architecture - LUT Contents, Ray Andraka
circular read address generator, ravindra kalla
- Re: circular read address generator, Stefan
- hi stefen, ravindra kalla
  - Re: hi stefen, Stefan
Xilinx Multiple Spartan 3, Brad Smallridge
- Re: Xilinx Multiple Spartan 3, coshzz
  - Re: Xilinx Multiple Spartan 3, Antti Lukats
- Re: Xilinx Multiple Spartan 3, Vladislav Muravin
  - Re: Xilinx Multiple Spartan 3, Peter Alfke
- Re: Xilinx Multiple Spartan 3, Brad Smallridge
  - Re: Xilinx Multiple Spartan 3, Vladislav Muravin
Modifying opb_bram under EDK, praetorian
- Re: Modifying opb_bram under EDK, Duane Clark
  - Re: Modifying opb_bram under EDK, praetorian
    - Re: Modifying opb_bram under EDK, Duane Clark
Spartan3 with WebPack?, Chris Carlen
- Re: Spartan3 with WebPack?, Brian Dam Pedersen
- Re: Spartan3 with WebPack?, John Adair
  - Re: Spartan3 with WebPack?, Chris Carlen
Xilinx Best Source for Reset, Brad Smallridge
- Re: Xilinx Best Source for Reset, Mike Treseler
  - Re: Xilinx Best Source for Reset, Nial Stewart
    - Re: Xilinx Best Source for Reset, Mike Treseler
    - Re: Xilinx Best Source for Reset, Brad Smallridge
    - Re: Xilinx Best Source for Reset, mk
    - Re: Xilinx Best Source for Reset, Nial Stewart
    - Re: Xilinx Best Source for Reset, Jonathan Bromley
    - Re: Xilinx Best Source for Reset, Nial Stewart
    - Re: Xilinx Best Source for Reset, Brad Smallridge
    - Re: Xilinx Best Source for Reset, mk
    - Re: Xilinx Best Source for Reset, Brad Smallridge
    - Re: Xilinx Best Source for Reset, Phil Hays
    - Re: Xilinx Best Source for Reset, mk
    - Re: Xilinx Best Source for Reset, Mike Treseler
- Re: Xilinx Best Source for Reset, Duane Clark
- Re: Xilinx Best Source for Reset, Vladislav Muravin
Bidirectional Bus problem with ModelSim., Telenochek
- Re: Bidirectional Bus problem with ModelSim., Brad Smallridge
- Re: Bidirectional Bus problem with ModelSim., Duane Clark
- Re: Bidirectional Bus problem with ModelSim., Vladislav Muravin
GNU Linker (MicroBlaze) / debugging problem, raybakk
- Re: GNU Linker (MicroBlaze) / debugging problem, Jon Beniston
Re: Doubts on Xilinx FPGA, vssumesh
- Re: Doubts on Xilinx FPGA, John_H
webcamera access with ML310, VB
problem with Xilinx OPB to OPB bridge, bazogec
Re: Digilent's JTAG-USB cable with chipscope, Antti Lukats
- Re: Digilent's JTAG-USB cable with chipscope, do_not_reply_to_this_addr
  - Re: Digilent's JTAG-USB cable with chipscope, Antti Lukats
    - Re: Digilent's JTAG-USB cable with chipscope, Antti Lukats
    - Re: Digilent's JTAG-USB cable with chipscope, Eric Smith
some virtexII clock pads are useless??, lik
- Re: some virtexII clock pads are useless??, Philip Freidin
  - Re: some virtexII clock pads are useless??, Victor
- Re: some virtexII clock pads are useless??, Vladislav Muravin
  - Re: some virtexII clock pads are useless??, Symon
    - Re: some virtexII clock pads are useless??, Vladislav Muravin
FPGA, ravindra kalla
- Re: FPGA, ALuPin
Re: How to import a netlist in VHDL, Gladiator
struggling with general digital design, Telenochek
- Re: struggling with general digital design, MM
  - Re: struggling with general digital design, vssumesh
  - Re: struggling with general digital design, Jon Beniston
    - Re: struggling with general digital design, ALuPin
    - Re: struggling with general digital design, vssumesh
    - Re: struggling with general digital design, Andy Peters
    - Re: struggling with general digital design, vssumesh
  - Re: struggling with general digital design, Andy Peters
  - Re: struggling with general digital design, Telenochek
    - Re: struggling with general digital design, Mike Treseler
    - Re: struggling with general digital design, MM
Altera Avalon Address format between Master & SDRAM controller?, pinod01
- Re: Altera Avalon Address format between Master & SDRAM controller?, kempaj
Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?, Kissingers
ISE webpack doesnt support Spartan xcs10, solution??, googlinggoogler
- Re: ISE webpack doesnt support Spartan xcs10, solution??, John Adair
- Re: ISE webpack doesnt support Spartan xcs10, solution??, Guenter
- Re: ISE webpack doesnt support Spartan xcs10, solution??, googlinggoogler
  - Re: ISE webpack doesnt support Spartan xcs10, solution??, googlinggoogler
  - Re: ISE webpack doesnt support Spartan xcs10, solution??, David Tweed
- Re: ISE webpack doesnt support Spartan xcs10, solution??, Pedro
Re: Triggering and reseting FF, vssumesh
About post synthesize, vssumesh
- Re: About post synthesize, vssumesh
  - Re: About post synthesize, vssumesh
    - Re: About post synthesize, Vladislav Muravin
    - Re: About post synthesize, vssumesh
    - Re: About post synthesize, Vladislav Muravin
    - Re: About post synthesize, vssumesh
    - Re: About post synthesize, Vladislav Muravin
Xilinx ISE WebPACK-7.1i on NetBSD, Chet Stemen
Farrow filter VHDL implementation?, Andrew Lohbihler
question about use SRAM on annapolis wildstarII board, fpga
- Re: question about use SRAM on annapolis wildstarII board, ALuPin
  - Re: question about use SRAM on annapolis wildstarII board, Karl
    - Re: question about use SRAM on annapolis wildstarII board, ALuPin
Spartan3 Done is not going high, Brad Smallridge
- Re: Spartan3 Done is not going high, skherich
  - Re: Spartan3 Done is not going high, Brad Smallridge
  - Re: Spartan3 Done is not going high, Brad Smallridge
VHDL 200x? when?, Michael
- Re: VHDL 200x? when?, Andy Peters
  - Re: VHDL 200x? when?, Joel Kolstad
Re: ChipScope Pro : how to set up trigger, pasacco
- Re: ChipScope Pro : how to set up trigger, pasacco
- Re: ChipScope Pro : how to set up trigger, Nenad
  - Re: ChipScope Pro : how to set up trigger, pasacco
  - Re: ChipScope Pro : how to set up trigger, pasacco
    - Re: ChipScope Pro : how to set up trigger, Nenad
    - Re: ChipScope Pro : how to set up trigger, pasacco
Re: XST and TCL support?, Guenter
- <Possible follow-ups>
- Re: XST and TCL support?, Ben Twijnstra
  - Re: XST and TCL support?, Brandon
    - Re: XST and TCL support?, gallen
Re: GLCKs on Spartan3, Stefan
- Re: GLCKs on Spartan3, jimwu88NOOOSPAM@xxxxxxxxx
re:Synplify 8.1 - View Synthesis Report, Hagen2
Re: simple SRAM memory controller on the Altera Nios Dev Kit (Cyclone ed), Tommy Thorn
- Re: simple SRAM memory controller on the Altera Nios Dev Kit (Cyclone ed), Duane Clark
Re: VHDL soft-core portability to Xilinx, Altera, Atmel...., Ben Popoola
2-bit RAM16X In a V2PRo, Jeremy Stringer
Re: Virtex4 local clock timing, Marc Randolph
- Re: Virtex4 local clock timing, johnp
Re: Delay Generators in FPGAs, Marc Randolph