comp.arch.fpga

• Date Index

---

• Digilent's JTAG-USB cable with chipscope, do_not_reply_to_this_addr
  • Re: Digilent's JTAG-USB cable with chipscope, Paul Hartke
• Logic lab programmer, geert
• chipscope and V2P problems, geoffrey wall
• XST and TCL support?, Brandon
  • Re: XST and TCL support?, Andy Peters
    • Re: XST and TCL support?, Jim Wu
• Synplify 8.1 - View Synthesis Report, Hagen2
• GLCKs on Spartan3, Stefan
  • Re: GLCKs on Spartan3, Vladislav Muravin
• Re: simple SRAM memory controller on the Altera Nios Dev Kit (Cyclone ed), Tommy Thorn
  • Re: simple SRAM memory controller on the Altera Nios Dev Kit (Cyclone ed), Duane Clark
• How to import a netlist in VHDL, beeraka@xxxxxxxxx
• How to pass parameters to do file in commandline when running vsim?, ckpun1978
  • Re: How to pass parameters to do file in commandline when running vsim?, Jonathan Bromley
    • Re: How to pass parameters to do file in commandline when running vsim?, ckpun1978
• dual port ram, Matthew Plante
• Delay Generators in FPGAs, Chris Carlen
  • Re: Delay Generators in FPGAs, Antti Lukats
  • Re: Delay Generators in FPGAs, John Larkin
    • Re: Delay Generators in FPGAs, Peter Alfke
      • Re: Delay Generators in FPGAs, Marc Randolph
      • Re: Delay Generators in FPGAs, austin
      • Re: Delay Generators in FPGAs, Jim Granville
• No clock signals found in this design... XST V2P, geoffrey wall
  • Re: No clock signals found in this design... XST V2P, Vladislav Muravin
• chipscope/impact Virtex4 problem, Tim Verstraete
  • Re: chipscope/impact Virtex4 problem, Antti Lukats
    • Re: chipscope/impact Virtex4 problem, Tim Verstraete
  • Re: chipscope/impact Virtex4 problem, Jim Wu
    • Re: chipscope/impact Virtex4 problem, Tim Verstraete
• stratix gx query, Kaalia Anthony
  • Re: stratix gx query, Ben Twijnstra
• wishbone core with ethernet, hierarchy / architecture, mwiesbock
• simulatable but not synthesizable (verifiable), pasacco
  • Re: simulatable but not synthesizable (verifiable), Jonathan Bromley
    • Re: simulatable but not synthesizable (verifiable), Gunther Mannigel
      • Re: simulatable but not synthesizable (verifiable), pasacco
• Reset and Power-On Reset Activation XCFxxP PROMs, Pablo Alvarez Sanchez
  • Re: Reset and Power-On Reset Activation XCFxxP PROMs, austin
    • Re: Reset and Power-On Reset Activation XCFxxP PROMs, Pablo Alvarez Sanchez
• bmm file and ramb16, Matthew Plante
  • Re: bmm file and ramb16, Antti Lukats
    • Re: bmm file and ramb16, Matthew Plante
      • Re: bmm file and ramb16, Antti Lukats
• question for Xilinx ppl, Vladislav Muravin
  • Re: question for Xilinx ppl, zeeman_be
    • Re: question for Xilinx ppl, Vladislav Muravin
• isplever and GAL, Strelnikov
  • Re: isplever and GAL, Teo
    • Re: isplever and GAL, Jim Granville
      • Re: isplever and GAL, Antti Lukats
    • Re: isplever and GAL, Strelnikov
• QuartusII 4.2 problem, Monica
  • Re: QuartusII 4.2 problem, Paul Solomon
    • Re: QuartusII 4.2 problem, skatoulas
• Datasheet error in the Altera Cyclone 2C8F256 pindescription, Rene Tschaggelar
  • Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription, Karl
  • Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription, Ben Twijnstra
    • Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription, Rene Tschaggelar
      • Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription, Thomas Entner
      • Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription, Ben Twijnstra
      • Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription, Vaughn Betz
      • Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription, Ben Twijnstra
  • Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription, Karl
• WEB Pack 7.1 and registry access, efim
• how to measure number of cycles in ISE6.3, Jack
  • Re: how to measure number of cycles in ISE6.3, Martin Thompson
• Conversion of ASIC RTL to FPGA RTL, sarath
  • Re: Conversion of ASIC RTL to FPGA RTL, usenet_10
  • Re: Conversion of ASIC RTL to FPGA RTL, Vladislav Muravin
  • Re: Conversion of ASIC RTL to FPGA RTL, Ben Twijnstra
    • Re: Conversion of ASIC RTL to FPGA RTL, neeraj_varma
• Xilinx Foundation ISE and WinXP/x64?, hpg
  • Re: Xilinx Foundation ISE and WinXP/x64?, Keith So
    • Re: Xilinx Foundation ISE and WinXP/x64?, Jim Wu
• ISE makes a mistake, skatoulas
  • Re: ISE makes a mistake, Mike Treseler
• LVDS problem/chipscope VIRTEX4, Yttrium
• The new IOBUF in Spartan-3E, George Mercury
  • Re: The new IOBUF in Spartan-3E, Daniel Koethe
• Asynchronous Priority comparator, llabakdas
• chipscope on opb bus, bazogec
  • Re: chipscope on opb bus, Antti Lukats
• [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?, uxello
  • Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?, Antti Lukats
    • Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?, uxello
    • Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?, MM
      • Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?, Antti Lukats
      • Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?, MM
      • Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?, Antti Lukats
• Confused with "task" keyword., Confused Frank
• Soft IPs licensing, hata
  • Re: Soft IPs licensing, Antti Lukats
  • Re: Soft IPs licensing -gpl, James Harry
• comprehension of clck to pad,clock to setup,etc, mike
  • Re: comprehension of clck to pad,clock to setup,etc, Vladislav Muravin
• Distributed Arithmetic Architecture - LUT Contents, Andrew FPGA
• Virtex4 local clock timing, johnp
• VHDL soft-core portability to Xilinx, Altera, Atmel...., Yaju Nagaonkar
  • Re: VHDL soft-core portability to Xilinx, Altera, Atmel...., Mike Treseler
    • Re: VHDL soft-core portability to Xilinx, Altera, Atmel...., Antti Lukats
      • Re: VHDL soft-core portability to Xilinx, Altera, Atmel...., Yaju Nagaonkar
      • Re: VHDL soft-core portability to Xilinx, Altera, Atmel...., Antti Lukats
• Virtex 2 Pro Routing Constraints, praetorian
  • Re: Virtex 2 Pro Routing Constraints, Antti Lukats
    • Re: Virtex 2 Pro Routing Constraints, Sven
• Free 8 bit micro for fpga, Teo
  • Re: Free 8 bit micro for fpga, austin
    • Re: Free 8 bit micro for fpga, Gabor
      • Re: Free 8 bit micro for fpga, Antti Lukats
      • Re: Free 8 bit micro for fpga, Jon Beniston
    • Re: Free 8 bit micro for fpga, Antti Lukats
      • Re: Free 8 bit micro for fpga, Jim Granville
  • Re: Free 8 bit micro for fpga, uxello
• How to implement Evolvable Hardware ?, apsolar
• OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Antti Lukats
  • Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Martin Schoeberl
    • Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Antti Lukats
      • Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Jim Granville
      • Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Antti Lukats
      • Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Jim Granville
      • Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Antti Lukats
      • Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Jim Granville
      • Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Antti Lukats
  • Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Franklin
    • Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Antti Lukats
      • Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now), Jim Granville
• Exact time-to-Failure data for FPGA devices, Amr Ahmadain
  • Re: Exact time-to-Failure data for FPGA devices, Peter Alfke
  • Re: Exact time-to-Failure data for FPGA devices, austin
    • Re: Exact time-to-Failure data for FPGA devices, Amr Ahmadain
      • Re: Exact time-to-Failure data for FPGA devices, Peter Alfke
      • Re: Exact time-to-Failure data for FPGA devices, Amr Ahmadain
      • Re: Exact time-to-Failure data for FPGA devices, Peter Alfke
• How to look inside a RAM memory, Giox
  • Re: How to look inside a RAM memory, ALuPin
    • Re: How to look inside a RAM memory, Giox
  • Re: How to look inside a RAM memory, jimwu88NOOOSPAM@xxxxxxxxx
• Excalibur full strip simulation on solaris., arie
  • Re: Excalibur full strip simulation on solaris., Antti Lukats
    • Re: Excalibur full strip simulation on solaris., Phil Hays
      • Re: Excalibur full strip simulation on solaris., Antti Lukats
      • Re: Excalibur full strip simulation on solaris., Phil Hays
      • Re: Excalibur full strip simulation on solaris., Antti Lukats
      • Re: Excalibur full strip simulation on solaris., arie
      • Re: Excalibur full strip simulation on solaris., arie
      • Re: Excalibur full strip simulation on solaris., Antti Lukats
      • Re: Excalibur full strip simulation on solaris., arie
      • Re: Excalibur full strip simulation on solaris., arie
• DCM., im.de
  • Re: DCM., Antti Lukats
  • Re: DCM., Jerzy Gbur
  • Re: DCM., dexue
    • Re: DCM., austin
  • Re: DCM., Vladislav Muravin
• Problems installing windrvr.o in Red Hat EL3..., SantaBarbara350Z
  • Re: Problems installing windrvr.o in Red Hat EL3..., Martin Thompson
    • Re: Problems installing windrvr.o in Red Hat EL3..., SantaBarbara350Z@xxxxxxxxx
• Fastest way to compute floating point log and exp, Marc Battyani
  • Re: Fastest way to compute floating point log and exp, Ray Andraka
    • Re: Fastest way to compute floating point log and exp, Marc Battyani
  • Re: Fastest way to compute floating point log and exp, Philip Freidin
    • Re: Fastest way to compute floating point log and exp, GMM50
      • Re: Fastest way to compute floating point log and exp, Ray Andraka
    • Re: Fastest way to compute floating point log and exp, Marc Battyani
  • Re: Fastest way to compute floating point log and exp, Kolja Sulimma
• Update contacts at Altera, Jedi
  • Re: Update contacts at Altera, Jedi
    • Re: Update contacts at Altera, Antti Lukats
      • Re: Update contacts at Altera, Jedi
      • Re: Update contacts at Altera, Vaughn Betz
• Transfert data to Memec Virtex II Pro Card from PC, jacques77
  • Re: Transfert data to Memec Virtex II Pro Card from PC, praetorian
    • Re: Transfert data to Memec Virtex II Pro Card from PC, Correlious
• parallel optic availability, Tullio Grassi
  • Re: parallel optic availability, Falk Brunner
    • Re: parallel optic availability, Tullio Grassi
  • Re: parallel optic availability, Franklin
• Overmapped, Stefan
  • Re: Overmapped, Philip Freidin
• Place Error, stbcasa
  • Re: Place Error, Gabor
• What a nice day for XLNX, ituspam@xxxxxxxxx
  • Re: What a nice day for XLNX, Andy Peters
• verilog to blif(lut), junaid
  • Re: verilog to blif(lut), Andy Peters
  • Re: verilog to blif(lut), Vladislav Muravin
    • Re: verilog to blif(lut), Antti Lukats
  • Re: verilog to blif(lut), jacob . bower
    • Re: verilog to blif(lut), Paul Leventis \(at home\)
  • Re: verilog to blif(lut), Vaughn Betz
• Xilinx software update?, Martin
  • Re: Xilinx software update?, austin
    • Re: Xilinx software update?, Marc Randolph
      • Re: Xilinx software update?, Martin
  • Re: Xilinx software update?, Bob Perlman
    • Re: Xilinx software update?, Martin
      • Re: Xilinx software update?, Gladiator
  • Re: Xilinx software update?, Hiding in Plain Sight
• DDR SDRAM on ML401, Nenad
  • Re: DDR SDRAM on ML401, Jim Wu
    • Re: DDR SDRAM on ML401, Nenad
      • Re: DDR SDRAM on ML401, jimwu88NOOOSPAM@xxxxxxxxx
• Does anyone have a NIOS Ethernet Development Kit?, brentkucera
  • Re: Does anyone have a NIOS Ethernet Development Kit?, Mike Treseler
    • Re: Does anyone have a NIOS Ethernet Development Kit?, Brent Kucera
      • Re: Does anyone have a NIOS Ethernet Development Kit?, Brent Kucera
• Heat Sink for Stratix, Patrick
• IP-cores for digital audio, Holger Blum
  • Re: IP-cores for digital audio, Al Clark
  • Re: IP-cores for digital audio, amyler
• Optimizing out a divide on altera cyclone fpga, Shanon Fernald
  • Re: Optimizing out a divide on altera cyclone fpga, Gary Pace
    • Re: Optimizing out a divide on altera cyclone fpga, allanherriman
      • Re: Optimizing out a divide on altera cyclone fpga, Shanon Fernald
      • Re: Optimizing out a divide on altera cyclone fpga, Shanon Fernald
      • Re: Optimizing out a divide on altera cyclone fpga, Ray Andraka
      • Re: Optimizing out a divide on altera cyclone fpga, Shanon Fernald
      • Re: Optimizing out a divide on altera cyclone fpga, allanherriman
• Creating Variable Delay for output signals in an XCV1000, John D. Davis
  • Re: Creating Variable Delay for output signals in an XCV1000, austin
    • Re: Creating Variable Delay for output signals in an XCV1000, John D. Davis
      • Re: Creating Variable Delay for output signals in an XCV1000, Peter Alfke
• FPGA + DIMM SDRAM, Nick
• All of the design is being optimized away and logic removed, azam
  • Re: All of the design is being optimized away and logic removed, Vladislav Muravin
    • Re: All of the design is being optimized away and logic removed, Ray Andraka
    • Re: All of the design is being optimized away and logic removed, azam
      • Re: All of the design is being optimized away and logic removed, Love Singhal
      • Re: All of the design is being optimized away and logic removed, Vladislav Muravin
      • Re: All of the design is being optimized away and logic removed, azam
  • <Possible follow-ups>
  • All of the design is being optimized away and logic removed, azam
• Generics of type time and XST synthesis, Brandon
  • Re: Generics of type time and XST synthesis, Andy Peters
• DDR SDRAM configuration, ALuPin
• Softcore based Rapid Protyping?, sarath1111
• Re: Using unregistered inputs in FSM, John Adair
• General-purpose STAPL Composer?, Alex Rast
  • Re: General-purpose STAPL Composer?, Laurent Gauch
  • Re: General-purpose STAPL Composer?, Daniel Leu
    • Re: General-purpose STAPL Composer?, Alex Rast
      • Re: General-purpose STAPL Composer?, Ralph Friedrich
      • Re: General-purpose STAPL Composer?, Alex Rast
• Virtex-4 hot-swappable?, JD_Design
  • Re: Virtex-4 hot-swappable?, austin
• Ones Count 64 bit on Xilinx in VHDL, Brad Smallridge
  • Re: Ones Count 64 bit on Xilinx in VHDL, John_H
    • Re: Ones Count 64 bit on Xilinx in VHDL, Brad Smallridge
      • Re: Ones Count 64 bit on Xilinx in VHDL, Peter Alfke
      • Re: Ones Count 64 bit on Xilinx in VHDL, Peter Alfke
      • Re: Ones Count 64 bit on Xilinx in VHDL, John_H
      • Re: Ones Count 64 bit on Xilinx in VHDL, Brad Smallridge
      • Re: Ones Count 64 bit on Xilinx in VHDL, John_H
    • Re: Ones Count 64 bit on Xilinx in VHDL, Brad Smallridge
  • Re: Ones Count 64 bit on Xilinx in VHDL, JJ
    • Re: Ones Count 64 bit on Xilinx in VHDL, JJ
      • Re: Ones Count 64 bit on Xilinx in VHDL, Peter Alfke
      • Re: Ones Count 64 bit on Xilinx in VHDL, JJ
      • Re: Ones Count 64 bit on Xilinx in VHDL, JJ
  • Re: Ones Count 64 bit on Xilinx in VHDL, Ray Andraka
  • Re: Ones Count 64 bit on Xilinx in VHDL, Vladislav Muravin
    • Re: Ones Count 64 bit on Xilinx in VHDL, Peter Alfke
      • Re: Ones Count 64 bit on Xilinx in VHDL, Ben Twijnstra
      • Re: Ones Count 64 bit on Xilinx in VHDL, Ray Andraka
  • Re: Ones Count 64 bit on Xilinx in VHDL, JustJohn
  • Re: Ones Count 64 bit on Xilinx in VHDL, Brad Smallridge
• Xilinx sysace + xmd -jprog options., tony.p.lee@xxxxxxxxx
  • Re: Xilinx sysace + xmd -jprog options., tony.p.lee@xxxxxxxxx
• ChipScope Pro : how to set up trigger, pasacco
  • Re: ChipScope Pro : how to set up trigger, Antti Lukats
    • Re: ChipScope Pro : how to set up trigger, pasacco
      • Re: ChipScope Pro : how to set up trigger, Nenad
      • Re: ChipScope Pro : how to set up trigger, pasacco
      • Re: ChipScope Pro : how to set up trigger, pasacco
      • Re: ChipScope Pro : how to set up trigger, Nenad
      • Re: ChipScope Pro : how to set up trigger, pasacco
      • Re: ChipScope Pro : how to set up trigger, Nenad
• Xilinx equivalent of simplify constrains., vssumesh
  • Re: Xilinx equivalent of simplify constrains., Antti Lukats
  • Re: Xilinx equivalent of simplify constrains., Vladislav Muravin
• ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1, Jens
  • Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1, Antti Lukats
    • Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1, pasacco
  • Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1, Vladislav Muravin
  • Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1, zeeman_be
• Power PC Stall ??, Vaggelis
• July 20th Altera Net Seminar: Stratix II Logic Density, Paul Leventis \(at home\)
  • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Peter Alfke
  • Re: July 20th Altera Net Seminar: Stratix II Logic Density, tim
    • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Antti Lukats
    • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Vaughn Betz
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Marc Randolph
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Paul Leventis \(at home\)
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Marc Randolph
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Paul Leventis \(at home\)
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Marc Randolph
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, tim
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, tim
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Henry Wong
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Paul Leventis \(at home\)
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Ray Andraka
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Peter Alfke
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Ray Andraka
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Paul Leventis \(at home\)
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Ray Andraka
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Vaughn Betz
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Paul Leventis \(at home\)
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, austin
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Peter Alfke
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Kees van Reeuwijk
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Peter Alfke
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Mike Treseler
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, austin
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, mk
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Andy Peters
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Thomas Entner
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Philip Freidin
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Ray Andraka
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Vaughn Betz
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, seannstifler69
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Paul Leventis
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Kolja Sulimma
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Paul Leventis
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Antti Lukats
      • Re: July 20th Altera Net Seminar: Stratix II Logic Density, Paul Leventis \(at home\)
• simulation troubles, zoinks@xxxxxxxxxxxxxxx
• Driving the FPGA output., vssumesh
  • Re: Driving the FPGA output., Antti Lukats
    • Re: Driving the FPGA output., Kolja Sulimma
• ethernet EMAC cores available for Microblaze, kurapati
• EDK 7.1 with ML401 (paging Antti), Pete Fraser
  • Re: EDK 7.1 with ML401 (paging Antti), John Williams
  • Re: EDK 7.1 with ML401 (paging Antti), Antti Lukats
  • Re: EDK 7.1 with ML401 (paging Antti), joe4702
• EHLO, board designers, Brannon
  • Re: EHLO, board designers, Antti Lukats
    • Re: EHLO, board designers, Ben Twijnstra
  • Re: EHLO, board designers, Joel Kolstad
  • Re: EHLO, board designers, Arash Salarian
    • Re: EHLO, board designers, Ray Andraka
  • Re: EHLO, board designers, John Adair
• sample for virtex4, chat
• Virtex-4 breaking the 1GHz clocking barrier in general purpose FPGA fabric (e.g non dedicated circuits), Antti Lukats
  • Re: Virtex-4 breaking the 1GHz clocking barrier in general purpose FPGA fabric (e.g non dedicated circuits), austin
• re:Hard Ethernet MAC for Virtex-4 FX12, kurapati
• pricing of Virtex-4, Vladislav Muravin
  • Re: pricing of Virtex-4, Antti Lukats
    • Re: pricing of Virtex-4, Vladislav Muravin
      • Re: pricing of Virtex-4, Peter Alfke
      • Re: pricing of Virtex-4, Vladislav Muravin
      • Re: pricing of Virtex-4, John Adair
      • Re: pricing of Virtex-4, Vladislav Muravin
• Red Hat Enterprise 64 bit and ISE WebPack, Marco
• Lattice MachXO is LAUNCHED NOW!, Antti Lukats
  • Re: Lattice MachXO is LAUNCHED NOW!, Unbeliever
    • Re: Lattice MachXO is LAUNCHED NOW!, Antti Lukats
    • Re: Lattice MachXO is LAUNCHED NOW!, Luc
      • Re: Lattice MachXO is LAUNCHED NOW!, Unbeliever
      • Re: Lattice MachXO is LAUNCHED NOW!, Luc
  • <Possible follow-ups>
  • Lattice MachXO is LAUNCHED NOW!, Antti Lukats
• setting XUP new board, elinore2005
  • Re: setting XUP new board, Paul Hartke
  • Re: setting XUP new board, Alex Gibson
    • Re: setting XUP new board, elinore2005
      • Re: setting XUP new board, el231bat
• Lab machine xmd/debugger install?, Michael Dales
  • Re: Lab machine xmd/debugger install?, John Adair
    • Re: Lab machine xmd/debugger install?, Michael Dales
• EDK and powerpc-eabi compiler, Mancini Stephane
• Sparan S3E availability update, Antti Lukats
• "Tbufs don't exist", Jack Falk
  • Re: "Tbufs don't exist", Antti Lukats
    • Re: "Tbufs don't exist", Bob Perlman
• chips with partial reconfig other than atmel & xilinx?, Jack Falk
  • Re: chips with partial reconfig other than atmel & xilinx?, Antti Lukats
• Serial vs Chipscope, pasacco
  • Re: Serial vs Chipscope, Antti Lukats
  • Re: Serial vs Chipscope, Mike Treseler
    • Re: Serial vs Chipscope, pasacco
• post-place & route simulation of simple project problem., coshzz
  • Re: post-place & route simulation of simple project problem., coshzz
  • Re: post-place & route simulation of simple project problem., Brijesh
    • Re: post-place & route simulation of simple project problem., coshzz
• Can't run Xilinx 7.1SP3 on FC3, B. Joshua Rosen
  • Re: Can't run Xilinx 7.1SP3 on FC3, Paul Hartke
    • Re: Can't run Xilinx 7.1SP3 on FC3, B. Joshua Rosen
• virtex 4 configuration error, abgoyal
• Interface Wi-Fi with FPGA, Gabster
• FPGA2006 Call for Papers -- ACM/SIGDA International Symposium on FPGAs, Guy Lemieux
• Compilation error with Synplify attribute, muthusnv
  • Re: Compilation error with Synplify attribute, Ken McElvain
• Linux Fedora and Xilinx ISE, Marco
  • Re: Linux Fedora and Xilinx ISE, jeff murphy
  • Re: Linux Fedora and Xilinx ISE, Marco
• Xilinx: Clock speeds 420MHz+ tested in Spartan-3, Antti Lukats
  • Re: Xilinx: Clock speeds 420MHz+ tested in Spartan-3, Unbeliever
    • Re: Xilinx: Clock speeds 420MHz+ tested in Spartan-3, Antti Lukats
• Plz send C compiler for picoblaze with manual, fahadislam2002
• Xilinx MPEG, Johan Riesbeck
• Virtex-4 5V tolerance, Heiko Kalte
  • Re: Virtex-4 5V tolerance, Antti Lukats
  • Re: Virtex-4 5V tolerance, austin
    • Re: Virtex-4 5V tolerance, Peter Alfke
  • re:Virtex-4 5V tolerance, Big Boy
• NIOS II + USB 2.0 host, bjskill
  • Re: NIOS II + USB 2.0 host, Antti Lukats
    • Re: NIOS II + USB 2.0 host, Antonio Pasini
      • Re: NIOS II + USB 2.0 host, Antti Lukats
      • Re: NIOS II + USB 2.0 host, bjskill
  • Re: NIOS II + USB 2.0 host, Rudolf Usselmann
    • Re: NIOS II + USB 2.0 host, bjskill
• How to Interface External Ram with FPGA, fahadislam2002
  • Re: How to Interface External Ram with FPGA, Correlious
• Bus Macros, praetorian
  • Re: Bus Macros, Gabor
    • Re: Bus Macros, praetorian
      • Re: Bus Macros, Gabor
      • Re: Bus Macros, Correlious
      • Re: Bus Macros, praetorian
• Reciprocal of improper fraction by using Divider ipcore, Joey Martin
• Doubts on Xilinx FPGA, vssumesh
  • Re: Doubts on Xilinx FPGA, Gabor
  • Re: Doubts on Xilinx FPGA, John_H
    • Re: Doubts on Xilinx FPGA, vssumesh
      • Re: Doubts on Xilinx FPGA, John_H
    • Re: Doubts on Xilinx FPGA, vssumesh
      • Re: Doubts on Xilinx FPGA, vssumesh
      • Re: Doubts on Xilinx FPGA, John_H
  • Re: Doubts on Xilinx FPGA, Andy Peters
    • Re: Doubts on Xilinx FPGA, Gabor
• Why cann't this block be synthesized in top level, Chinix
  • Re: Why cann't this block be synthesized in top level, ALuPin
    • Re: Why cann't this block be synthesized in top level, Chinix
      • Re: Why cann't this block be synthesized in top level, Chinix
      • Re: Why cann't this block be synthesized in top level, Gabor
      • Re: Why cann't this block be synthesized in top level, Chinix
      • Re: Why cann't this block be synthesized in top level, RaKa
• why my programm has no response after i added some opb_bram_if_ctrl core my project?, mlpei279
  • Re: why my programm has no response after i added some opb_bram_if_ctrl core my project?, Antti Lukats
• Wanted: I2C RAM pre-loader VHDL module, scd
  • Re: Wanted: I2C RAM pre-loader VHDL module, Antti Lukats
    • Re: Wanted: I2C RAM pre-loader VHDL module, Kryten
• Modulo division in Verilog, Paul Solomon
  • Re: Modulo division in Verilog, mk
    • Re: Modulo division in Verilog, Paul Solomon
  • Re: Modulo division in Verilog, John_H
    • Re: Modulo division in Verilog, Paul Solomon
      • Re: Modulo division in Verilog, John_H
      • Re: Modulo division in Verilog, Paul Solomon
      • Re: Modulo division in Verilog, John_H
      • Re: Modulo division in Verilog, Vaughn Betz
• Wanted Actel ProAsic RAM VHDL models, scd
  • Re: Wanted Actel ProAsic RAM VHDL models, Hans
• Reading a PS/2 mouse, greenplanet
  • Re: Reading a PS/2 mouse, greenplanet
    • Re: Reading a PS/2 mouse, Jeremy Stringer
      • Re: Reading a PS/2 mouse, greenplanet
      • Re: Reading a PS/2 mouse, Jeremy Stringer
  • re:Reading a PS/2 mouse, Big Boy
    • Re: Reading a PS/2 mouse, greenplanet
• Virtex 300: what could cause pin to short?, Bob Myers
  • Re: Virtex 300: what could cause pin to short?, Peter Alfke
  • Re: Virtex 300: what could cause pin to short?, Peter Alfke
  • Re: Virtex 300: what could cause pin to short?, Marc
  • Re: Virtex 300: what could cause pin to short?, John_H
  • Re: Virtex 300: what could cause pin to short?, Jon Elson
• MachXO - not released, but already supported by Aldec !!, Antti Lukats
• virtex 4 : how can I know the clock region coverage?, linq936
  • Re: virtex 4 : how can I know the clock region coverage?, Antti Lukats
  • Re: virtex 4 : how can I know the clock region coverage?, Antti Lukats
• IEEE1532 question, with Xilinx devices, Antti Lukats
• ise 7.1 Input clk is never used., jeff murphy
  • Re: ise 7.1 Input clk is never used., Antti Lukats
  • Re: ise 7.1 Input clk is never used., Andy Peters
  • Re: ise 7.1 Input clk is never used., raghurash
  • Re: ise 7.1 Input clk is never used., ALuPin
    • Re: ise 7.1 Input clk is never used., jeff murphy
      • Re: ise 7.1 Input clk is never used., Martin Thompson
• Problems programing FPGAs.., Shai
  • Re: Problems programing FPGAs.., Antti Lukats
  • Re: Problems programing FPGAs.., Rene Tschaggelar
• Implement a JTAG controller in an FPGA, irish
  • Re: Implement a JTAG controller in an FPGA, Antti Lukats
  • Re: Implement a JTAG controller in an FPGA, Luc
    • Re: Implement a JTAG controller in an FPGA, Antti Lukats
• edif version generated by xilinx ISE 6.2, Hassan Atat
  • Re: edif version generated by xilinx ISE 6.2, Jon Beniston
• Safe State Machine Design in AHDL, jjlindula@xxxxxxxxxxx
  • Re: Safe State Machine Design in AHDL, Arash Salarian
• Observations on passing clock constraints through DCM in Synplify 8.1, Aj
  • <Possible follow-ups>
  • Observations on passing clock constraints through DCM in Synplify 8.1, Aj
• 16-bit Acesses on ISA bus, amko
  • Re: 16-bit Acesses on ISA bus, Peter C. Wallace
  • Re: 16-bit Acesses on ISA bus, Arash Salarian
• Xilinx Conversion 3.1 --> 6.1, Max
  • Re: Xilinx Conversion 3.1 --> 6.1, Gabor
    • Re: Xilinx Conversion 3.1 --> 6.1, Max
      • Re: Xilinx Conversion 3.1 --> 6.1, Gabor
      • Re: Xilinx Conversion 3.1 --> 6.1, Alex Gibson
  • Re: Xilinx Conversion 3.1 --> 6.1, John Adair
• Xilinx PLEASE HELP, Antti Lukats
  • Re: Xilinx PLEASE HELP, Antti Lukats
    • Re: Xilinx PLEASE HELP, Antti Lukats
      • Re: Xilinx PLEASE HELP, thanks issue solved by reverse engineering..., Antti Lukats
• Re: Xilinx MAP problem (>1 External Macro Output Pin on single net), Ian
  • <Possible follow-ups>
  • Re: Xilinx MAP problem (>1 External Macro Output Pin on single net), Andy Peters
    • Re: Xilinx MAP problem (>1 External Macro Output Pin on single net), Ian
      • Re: Xilinx MAP problem (>1 External Macro Output Pin on single net), Pete Sedcole
• Clock recovery in FPGA at 300 MHZ, praveen . kantharajapura
  • Re: Clock recovery in FPGA at 300 MHZ, Ben Twijnstra
    • Re: Clock recovery in FPGA at 300 MHZ, Vaughn Betz
    • Re: Clock recovery in FPGA at 300 MHZ, praveen . kantharajapura
• Quartus 5.0sp1 -- Error: Unexpected error in JTAG server -- error code 33, Tommy Thorn
  • Re: Quartus 5.0sp1 -- Error: Unexpected error in JTAG server -- error code 33, Antti Lukats
• Unrolled Pipeline Implementation, Paul Solomon
  • Re: Unrolled Pipeline Implementation, Ray Andraka
  • Re: Unrolled Pipeline Implementation, John_H
  • Re: Unrolled Pipeline Implementation, Arash Salarian
• QII simulation annoyance, tns1
  • Re: QII simulation annoyance, ALuPin
    • Re: QII simulation annoyance, tns
  • Re: QII simulation annoyance, Mike Treseler
    • Re: QII simulation annoyance, tns
      • Re: QII simulation annoyance, Andy Peters
  • Re: QII simulation annoyance, GMM50
    • Re: QII simulation annoyance, tns1
      • Re: QII simulation annoyance, Andy Peters
      • Re: QII simulation annoyance, tns
    • Re: QII simulation annoyance, Markus Knauss
  • Re: QII simulation annoyance, Vaughn Betz
    • Re: QII simulation annoyance, tns
      • Re: QII simulation annoyance, Vaughn Betz
• Testbenching and verification, Paul Solomon
  • Re: Testbenching and verification, Andy Peters
  • Re: Testbenching and verification, Arash Salarian
    • Re: Testbenching and verification, Vaughn Betz
• Bazix introduce FPGA based One Chip computer system, Sander Zuidema
  • Re: Bazix introduce FPGA based One Chip computer system, Jedi
    • Re: Bazix introduce FPGA based One Chip computer system, Sander Zuidema
      • Re: Bazix introduce FPGA based One Chip computer system, Antti Lukats
      • Re: Bazix introduce FPGA based One Chip computer system, Sander Zuidema
      • Re: Bazix introduce FPGA based One Chip computer system, Antti Lukats
• Any Scope/LogicAnalyzer that can decode 8b/10b signals in the Rocket IO?, tony . p . lee
  • Re: Any Scope/LogicAnalyzer that can decode 8b/10b signals in the Rocket IO?, Antti Lukats
• output-value isn't stored, Manfred Balik
  • Re: output-value isn't stored, Gabor
  • Re: output-value isn't stored, Sean Durkin
    • Re: output-value isn't stored, Andy Peters
      • Re: output-value isn't stored, Sean Durkin
• stupid question about XPS peripheral filenames, zoinks@xxxxxxxxxxxxxxx
  • Re: stupid question about XPS peripheral filenames, Antti Lukats
• Wishbone RTL simulator, hata
  • Re: Wishbone RTL simulator, Antti Lukats
    • Re: Wishbone RTL simulator, hata
      • Re: Wishbone RTL simulator, Rudolf Usselmann
• new PLD and FPGA devices from Lattice, Antti Lukats
  • Re: new PLD and FPGA devices from Lattice, Thomas Entner
• Search for FPGA, Thomas Reinemann
  • Re: Search for FPGA, Antti Lukats
    • Re: Search for FPGA, Thomas Stanka
  • Re: Search for FPGA, Michael Bodenbach
  • Re: Search for FPGA, John Adair
    • Re: Search for FPGA, Gabor
      • Re: Search for FPGA, John Adair
• Quartus Timing Issues, Paul Solomon
  • Re: Quartus Timing Issues, Mike Treseler
    • Re: Quartus Timing Issues, Paul Solomon
      • Re: Quartus Timing Issues, Vaughn Betz
• design does not fit in device, nahum_barnea
  • Re: design does not fit in device, Falk Brunner
    • Re: design does not fit in device, Nahum Barnea
  • Re: design does not fit in device, John Adair
• Altera QII WE Tutorials, farnel
  • Re: Altera QII WE Tutorials, Jim Granville
  • Re: Altera QII WE Tutorials, Vaughn Betz
• Rocket IO failure after power cycle., tony.p.lee@xxxxxxxxx
  • Re: Rocket IO failure after power cycle., Marko
    • Re: Rocket IO failure after power cycle., Jerzy Gbur
• Announce: Impulse C-to-RTL Version 2 now available, David Pellerin
  • Re: Announce: Impulse C-to-RTL Version 2 now available, Mike Treseler
    • Re: Announce: Impulse C-to-RTL Version 2 now available, JJ
      • Re: Announce: Impulse C-to-RTL Version 2 now available, Hans
      • Re: Announce: Impulse C-to-RTL Version 2 now available, David Pellerin
      • Re: Announce: Impulse C-to-RTL Version 2 now available, gallen
      • Re: Announce: Impulse C-to-RTL Version 2 now available, Daniel Leu
• Ethernet reference design for ML310?, Joseph
  • Re: Ethernet reference design for ML310?, Joseph
    • Re: Ethernet reference design for ML310?, Mike Treseler
      • Re: Ethernet reference design for ML310?, Joseph
• Xilinx ISE 7.1 : Macro search path in Transalate, PL
  • Re: Xilinx ISE 7.1 : Macro search path in Transalate, Duane Clark
• Timespec for DCM outputs (Spartan 3) ?, Paul Boven
  • Re: Timespec for DCM outputs (Spartan 3) ?, Falk Brunner
    • Re: Timespec for DCM outputs (Spartan 3) ?, Paul Boven
  • Re: Timespec for DCM outputs (Spartan 3) ?, Vladislav Muravin
    • Re: Timespec for DCM outputs (Spartan 3) ?, Paul Boven
      • Re: Timespec for DCM outputs (Spartan 3) ?, Philip Freidin
      • Re: Timespec for DCM outputs (Spartan 3) ?, Dave
      • Re: Timespec for DCM outputs (Spartan 3) ?, Symon
• Running prog from PROM, Joey
  • Re: Running prog from PROM, John Adair
  • Re: Running prog from PROM, Michael Bodenbach
    • Re: Running prog from PROM, Joey
      • Re: Running prog from PROM, m . bodenbach
      • Re: Running prog from PROM, Joey
  • ISE 7.1 SP3, Spartan3-E readiness ??, Antti Lukats
    • Re: ISE 7.1 SP3, Spartan3-E readiness ??, Antti Lukats
• FORGET THE IPOD IRIVER OR RIO MP3 MP4 PLAYER. THE TCG DIVAS WANT TO TELL YOU ABOUT THE M500 PORTABLE DIGITAL MEDIA CENTER CALL 504 914 9965 RIGHT NOW, techcom
• Possible bug in Vertex-4 Rocket-IO?, shuo . huang
  • Re: Possible bug in Vertex-4 Rocket-IO?, Marko
    • Re: Possible bug in Vertex-4 Rocket-IO?, shuo . huang
      • Re: Possible bug in Vertex-4 Rocket-IO?, Marko
      • Re: Possible bug in Vertex-4 Rocket-IO?, shuo . huang
      • Re: Possible bug in Vertex-4 Rocket-IO?, Marko
      • Re: Possible bug in Vertex-4 Rocket-IO?, shuo . huang
      • Re: Possible bug in Vertex-4 Rocket-IO?, Marko
      • Re: Possible bug in Vertex-4 Rocket-IO?, shuo . huang
      • Re: Possible bug in Vertex-4 Rocket-IO?, shuo . huang
• Xilinx V2Pro reconfiguration, Sven
• Ray Andraka when will your book be on store???, stud_lang_jap
  • Re: Ray Andraka when will your book be on store???, Ray Andraka
    • Re: Ray Andraka when will your book be on store???, stud_lang_jap
      • Re: Ray Andraka when will your book be on store???, Yttrium
• Stacked Die devices, Jim Granville
• Re: microblaze and 64 bit memory over PLB bus, krishna1234
• Re: XST: setting top-level generics, Ray Andraka
  • Re: XST: setting top-level generics, Andy Peters
• Re: Direct audio output from FPGA pins, Ray Andraka
• Resampling in FPGA with irrational or large rational ratios, bgaughan
  • Re: Resampling in FPGA with irrational or large rational ratios, Greg Berchin
• Re: Small FPGA, Carsten
• Max Sample Rate for Signal Tap in Altera Quartus?, jjlindula@xxxxxxxxxxx
  • Re: Max Sample Rate for Signal Tap in Altera Quartus?, Peter Sommerfeld
    • Re: Max Sample Rate for Signal Tap in Altera Quartus?, jjlindula@xxxxxxxxxxx
      • Re: Max Sample Rate for Signal Tap in Altera Quartus?, Thomas Entner
      • Re: Max Sample Rate for Signal Tap in Altera Quartus?, jjlindula@xxxxxxxxxxx
      • Re: Max Sample Rate for Signal Tap in Altera Quartus?, Vaughn Betz
• Verilog Coding Guidelines, Pistony2k
  • Re: Verilog Coding Guidelines, lardonna
  • <Possible follow-ups>
  • Verilog Coding Guidelines, Pistony2k
• QAM 64 implementation on a FPGA board, Kaalia Anthony
• Bit serial, book, other info???, Elektro
  • Re: Bit serial, book, other info???, Philip Freidin
  • Re: Bit serial, book, other info???, Ray Andraka
    • Re: Bit serial, book, other info???, Elektro
      • Re: Bit serial, book, other info???, temp
• aurora reliability, katherine
  • Re: aurora reliability, Duane Clark
    • Re: aurora reliability, katherine
      • Re: aurora reliability, Austin Lesea
      • Re: aurora reliability, Martin Thompson
      • Re: aurora reliability, katherine
• Recommend www.edaboard.com, Davy
  • Re: Recommend www.edaboard.com, jai.dhar@xxxxxxxxx
• SELV - power supply specification, vssumesh
  • Re: SELV - power supply specification, fred
    • Re: SELV - power supply specification, vssumesh
      • Re: SELV - power supply specification, fred
• Problems with Timing Simulation, ALuPin
  • Re: Problems with Timing Simulation, Ben Jones
    • Re: Problems with Timing Simulation, ALuPin
      • Re: Problems with Timing Simulation, ALuPin
      • Re: Problems with Timing Simulation, Ben Jones
      • Re: Problems with Timing Simulation, ALuPin
      • Re: Problems with Timing Simulation, Ben Jones
• Re: ppc 405 in debug halt mode, jagadeesh
• Re: Xilinx Virtex 4 device technology, Kolja Sulimma
  • Re: Xilinx Virtex 4 device technology, Austin Lesea
• about fast adder, Giox
  • Re: about fast adder, Sylvain Munaut
    • Re: about fast adder, Giox
      • Re: about fast adder, des00
      • Re: about fast adder, Giox
      • Re: about fast adder, John_H
      • Re: about fast adder, des00
      • Re: about fast adder, Giox
      • Re: about fast adder, Sylvain Munaut
      • Re: about fast adder, Giox
      • Re: about fast adder, JJ
      • Re: about fast adder, Marko
• Actel vs. Xilinx and Altera, Joel Kolstad
  • Re: Actel vs. Xilinx and Altera, Ed McGettigan
  • Re: Actel vs. Xilinx and Altera, Hans
    • Re: Actel vs. Xilinx and Altera, Joel Kolstad
• Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?, azam
  • Re: Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?, Jim Wu
  • Re: Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?, Austin Lesea
• for sale: two spartan-3 dev boards, $50 each (normally $100), Adam Megacz
• PC104 (ISA) bus in FPGA (Spatan 2E), amko
  • Re: PC104 (ISA) bus in FPGA (Spatan 2E), Gabor
  • Re: PC104 (ISA) bus in FPGA (Spatan 2E), Johan Bernspång
  • Re: PC104 (ISA) bus in FPGA (Spatan 2E), Peter Wallace
• Cheking out Linux Kernel Source, Sewook Wee
  • Re: Cheking out Linux Kernel Source, praetorian
  • Re: Cheking out Linux Kernel Source, Peter Ryser
• Spartan3 pci above 33MHz, RobJ
  • Re: Spartan3 pci above 33MHz, colin
• Spartan II 2s200 PCI Board, stbcasa
  • Re: Spartan II 2s200 PCI Board, Eric Smith
  • Re: Spartan II 2s200 PCI Board, Gabor
• Triggering and reseting FF, vssumesh
  • Re: Triggering and reseting FF, Vladislav Muravin
• Re: Spartan-3e order of availability?, oen_no_spam
  • Re: Spartan-3e order of availability?, Andrew FPGA
    • Re: Spartan-3e order of availability?, Peter Alfke
      • Re: Spartan-3e order of availability?, oen_no_spam
• virtex4 evaluation board, hata
  • Re: virtex4 evaluation board, Antti Lukats
    • Re: virtex4 evaluation board, hata
• Program from external memory, Joey
  • Re: Program from external memory, Joey
  • Re: Program from external memory, Andi
    • Re: Program from external memory, Joey
    • Re: Program from external memory, Peter Ryser
      • Re: Program from external memory, Joey
      • Re: Program from external memory, Joey
• PowerPC interrupt, Joey
  • Message not available
    • Re: PowerPC interrupt, Joey
  • Re: PowerPC interrupt, Andi
    • Re: PowerPC interrupt, Joey
• EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a, Nju Njoroge
  • Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a, ALuPin
  • Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a, Duane Clark
    • Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a, Nju Njoroge
      • Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a, Nju Njoroge
• fastest FPGA speed grade?, Dave
  • Re: fastest FPGA speed grade?, Jon Beniston
    • Re: fastest FPGA speed grade?, Antti Lukats
  • Re: fastest FPGA speed grade?, Paul Leventis \(at home\)
    • Re: fastest FPGA speed grade?, Jon Beniston
      • Re: fastest FPGA speed grade?, Nicholas Weaver
      • Re: fastest FPGA speed grade?, Peter Alfke
      • Re: fastest FPGA speed grade?, Falk Brunner
      • Re: fastest FPGA speed grade?, Nicholas Weaver
      • Re: fastest FPGA speed grade?, Falk Brunner
    • Re: fastest FPGA speed grade?, Ray Andraka
      • Re: fastest FPGA speed grade?, Falk Brunner
      • Re: fastest FPGA speed grade?, Andy Peters
  • Re: fastest FPGA speed grade? Not the only measure, but ..., Austin Lesea
    • Re: fastest FPGA speed grade? Not the only measure, but ..., Martin Thompson
      • Re: fastest FPGA speed grade? Not the only measure, but ..., Austin Lesea
      • Re: fastest FPGA speed grade? Not the only measure, but ..., sean
      • Re: fastest FPGA speed grade? Not the only measure, but ..., Paul Leventis \(at home\)
  • Re: fastest FPGA speed grade?, B. Joshua Rosen
  • Re: fastest FPGA speed grade?, Dave
• Re: interpolation in FPGA, jimgeorge at gmail dot com
• VHDL Clock Domains, Brad Smallridge
  • Re: VHDL Clock Domains, Vladislav Muravin
    • Re: VHDL Clock Domains, ALuPin
      • Re: VHDL Clock Domains, Mike Treseler
    • Re: VHDL Clock Domains, Duane Clark
      • Re: VHDL Clock Domains, Duane Clark
  • Re: VHDL Clock Domains, Paul Leventis \(at home\)
• Stratix open-drain pins, ernie
  • Re: Stratix open-drain pins, Sylvain Munaut
  • Re: Stratix open-drain pins, Rob
    • Re: Stratix open-drain pins, ernie
      • Re: Stratix open-drain pins, Mike Treseler
      • Re: Stratix open-drain pins, ernie
• Re: xp3/xp6 in ispLever, chrisawest
• Re: aurora framing, Nanditha
• Re: Individual study-activity on FPGA's - which subsubject?, Yaju N
• Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion problem), Antti Lukats
  • re:Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion pro, elcielo
    • Re: re:Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion pro, Antti Lukats
• VPR fundaes, junaid
  • Re: VPR fundaes, Paul Leventis \(at home\)
  • Re: VPR fundaes, Vaughn Betz
• PS/2 interface, greenplanet
  • Re: PS/2 interface, Hernán Sánchez
    • Re: PS/2 interface, greenplanet
      • Re: PS/2 interface, Dave Vanden Bout
      • Re: PS/2 interface, greenplanet
• Connecting ADC to Opb_Spi core, Marco
  • Re: Connecting ADC to Opb_Spi core, Antti Lukats
    • Re: Connecting ADC to Opb_Spi core, Marco
      • Re: Connecting ADC to Opb_Spi core, Antti Lukats
      • Re: Connecting ADC to Opb_Spi core, Marco
      • Re: Connecting ADC to Opb_Spi core, Antti Lukats
      • Re: Connecting ADC to Opb_Spi core, Marco
      • Re: Connecting ADC to Opb_Spi core, Sylvain Munaut
• Re: proth siever in FPGA?, Philip Freidin
  • Re: proth siever in FPGA? [LONG], Alex
• Re: Maintaining a Pipeline, valentin tihomirov
• Virtex-2 Pro: Configuration Frames, Sven
  • Re: Virtex-2 Pro: Configuration Frames, praetorian
• Re: Low cost altera board, John Miles
• Re: Problem for xilinx!!!, Peter Alfke
• Ethernet FPGA development board, jai.dhar@xxxxxxxxx
  • Re: Ethernet FPGA development board, jimgeorge at gmail dot com
    • Re: Ethernet FPGA development board, jai.dhar@xxxxxxxxx
• Re: FPGA development board - urgently, Pierrick
• nios2 toolchain sources..., Jedi
  • Re: nios2 toolchain sources..., Ben Twijnstra
    • Re: nios2 toolchain sources..., Jon Beniston
      • Re: nios2 toolchain sources..., Jedi
      • Re: nios2 toolchain sources..., Jedi
      • Re: nios2 toolchain sources..., Antti Lukats
      • Re: nios2 toolchain sources..., Ben Twijnstra
      • Re: nios2 toolchain sources..., Jedi
      • Re: nios2 toolchain sources..., Jon Beniston
  • <Possible follow-ups>
  • NIOS2 toolchain sources..., Jedi
    • Re: NIOS2 toolchain sources..., Antti Lukats
      • Re: NIOS2 toolchain sources..., Jedi
• EDK 6.3, Xilinx ML40x ML402, XBD files, Allan Willcox
  • Re: EDK 6.3, Xilinx ML40x ML402, XBD files, abgoyal
    • Re: EDK 6.3, Xilinx ML40x ML402, XBD files, Johan Bernspång
    • Re: EDK 6.3, Xilinx ML40x ML402, XBD files, Allan Willcox
• Call for FPGAworld 2005, david
• Xilinx IOB flop mapping vs. -bp switch, schellho
  • Re: Xilinx IOB flop mapping vs. -bp switch, Bret Wade
• Re: Xilinx: XST synchronous FIFO using BRAMs, Göran Bilski
  • Re: Xilinx: XST synchronous FIFO using BRAMs, sidney
  • <Possible follow-ups>
  • Re: Xilinx: XST synchronous FIFO using BRAMs, Unbeliever
    • Re: Xilinx: XST synchronous FIFO using BRAMs, sidney
  • Re: Xilinx: XST synchronous FIFO using BRAMs, Alvin Andries
    • Re: Xilinx: XST synchronous FIFO using BRAMs, Alvin Andries
      • Re: Xilinx: XST synchronous FIFO using BRAMs, sidney
      • Re: Xilinx: XST synchronous FIFO using BRAMs, Alvin Andries
    • Re: Xilinx: XST synchronous FIFO using BRAMs, sidney
      • Re: Xilinx: XST synchronous FIFO using BRAMs, Alvin Andries
      • Re: Xilinx: XST synchronous FIFO using BRAMs, Peter Alfke
      • Re: Xilinx: XST synchronous FIFO using BRAMs, sidney
      • Re: Xilinx: XST synchronous FIFO using BRAMs, Peter Alfke
      • Re: Xilinx: XST synchronous FIFO using BRAMs, Andy Peters
      • Re: Xilinx: XST synchronous FIFO using BRAMs, Martin Thompson
      • Re: Xilinx: XST synchronous FIFO using BRAMs, Alvin Andries
      • Re: Xilinx: XST synchronous FIFO using BRAMs, Peter Alfke
  • Re: Xilinx: XST synchronous FIFO using BRAMs, Vladislav Muravin
• Re: read & write on SDRAM speed with PPC 300 MHz, Pierre
• Re: Clock buffering in VirtexE FPGA, vssumesh
  • <Possible follow-ups>
  • Re: Clock buffering in VirtexE FPGA, bobrics
    • Re: Clock buffering in VirtexE FPGA, Ben Jones
      • Re: Clock buffering in VirtexE FPGA, bobrics
      • Re: Clock buffering in VirtexE FPGA, Peter Alfke
• Re: vhdl source code cross reference tool, Martin Thompson
• Re: ModelSim Timing Simulation Signal Names, Jonathan Bromley
  • Re: ModelSim Timing Simulation Signal Names, PeterC
    • Re: ModelSim Timing Simulation Signal Names, Phil Hays
      • Re: ModelSim Timing Simulation Signal Names, PeterC
      • Re: ModelSim Timing Simulation Signal Names, Phil Hays
      • Re: ModelSim Timing Simulation Signal Names, PeterC
  • <Possible follow-ups>
  • Re: ModelSim Timing Simulation Signal Names, Brian Philofsky

• Security
• UNIX
• Linux
• Coding
• Usenet

• Archive
• About
• Privacy
• Search
• Imprint

newsgroups.derkeiler.com  > Archive  > Comp  > comp.arch.fpga  > 2005-07