Hello, I am pretty new to working with FPGAs and verilog in general but have a
decent knowledge of programming, and Im trying to grasp the whole
concept of working with the wishbone, as well as verilog architecture.
I have the wishbone commax core and the ethernet ip core from
opencores.org, and im wondering how to go about setting up a basic
system to have some ethernet communication coming from my board which
currently is a Virtex-4 board , with a PHY chip built onto it. I know
the cores themselves already have a great setup, but im still unclear
on how to just place it all together. Im going to keep trying to play
around with it more and dig around more to see exactly how to do this,
but im the meaintime some sort of basic example of how to go about
setting it up would be greatly appreciated. Im not looking for code as
much as im looking for just a genereal layout of the hierarchy that I
could use in ISE (which im using for programming atm).
wishbone core with ethernet, hierarchy / architecture ... concept of working with the wishbone, as well as verilog architecture.... I have the wishbone commax core and the ethernet ip core from ... currently is a Virtex-4 board, with a PHY chip built onto it. ... could use in ISE (which im using for programming atm).... (comp.lang.verilog)
Re: wishbone core with ethernet, hierarchy / architecture ... I am pretty new to working with FPGAs and verilog in general but have a decent knowledge of programming, and Im trying to grasp the whole concept of working with the wishbone, as well as verilog architecture. ... I have the wishbone commax core and the ethernet ip core from opencores.org, and im wondering how to go about setting up a basic system to have some ethernet communication coming from my board which currently is a Virtex-4 board, with a PHY chip built onto it. ... But with any system design, you need to think about what devices that you need to put on the bus, how fast the bus will be running, and bandwidth issues. ... (comp.lang.verilog)
Re: "The Problem with Threads" - IEEEs Computer magazine article ... So, sure, if your exclusive target is single core computer systems, like traditional single core/single processor PCs, then threads offer nothing more than a decent programming abstraction for concurrent I/O management. ... and any form of temporal determinism is both difficult and extremely expensive. ... (comp.programming.threads)
Re: Raggedstone specifications ... ... >USB1.1 - Interface only (core needs to be implemented in FPGA) ... >got the opencores PCI working as well. ... I don't know the driver status on ... Is the Jungo driver needed only for programming?... (comp.arch.fpga)
Re: OO Forth System? ... in Forth (I think this would add useless complexity to the already very ... are not simply talking about OO ad-ons to the Forth core,... entering the OO world of structure also and to define a linked lists as ... IMO OO means just programming with structured data and methods. ... (comp.lang.forth)
