Re: Doubts on Xilinx FPGA

Internal BlockRAMs will initialize to zero unless you specify other values.
Some BlockRAM outputs (but not on Virtex-E) have an initial state for the
synchronous output specifiable.

The initial state of the registers is a little less obvious.
If a register is preset without a clear or set without a reset (using the
S/R input) the register will initialize high.
If a register isn't preset or set, it will initialize low. This includes
registers that are reset, cleared, or have no S/R control.

I use the terms "preset" and "clear" for asynchronous events and "set" and
"reset" for synchronous.


"vssumesh" <vssumesh_asic@xxxxxxxxx> wrote in message
news:1121435487.213730.287320@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
> What will be the status of F/F and internal block RAMs of VirtexE FPGA
> if i do not specify any initial condition. Can i assume that it is zero
> ?


.

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