New Microprocessor architecture

Hi everyone,

I have a new idea about microprocessor achitecture. I propose here so
that others can judge it. In my point of view, its performance lies
between current microprocessors and FPGA. In the best case, its
performance can reach as high as FPGA's. It is clear that FPGA is much
faster than microprocessor (if we compare FPGA prototype and software
simulation). Hence, I believe that my proposed processor would be many
times faster than current processors.

The basic idea is following. CPU is very flexible, it can run any
instruction in any order. In other words, its operation is dynamic.
However, it is slow because instructions are implemented sequencially.
FPGA is unflexible (after configuring it we can use for only one
application) (in other words, its operation is static) but it is very
fast because all slides run simultaneously. The key idea here is that
when CPU runs instructions within loops its operations is partially
static. The CPU repeats its operation for many times. Hence, it is
possible that we fetch instructions within loops into one array of
processsing elements and process in FPGA manner. That surely increases
the performance.

Although my proposed arechitecture is superior only when the CPU runs
instructions within loops, I can prove that most of time, CPU run
instructions within loops. I give here one example. A CPU run one
program in 1 hour. The size of program is 1GB. 90% of program code is
out of loop. We can fetch 10MB code in one second and there is no
stall. In this case the time to run instructions out of loops is:
1000*0.9/10=90 seconds. The time to run instructions within loops is
3600-90=3500 seconds. According to Amdahl's law, the improvement of a
big fraction results the considerable improvement of the complete
system.

Beside the said key idea, I also have some techniques to make the new
architecture compatible with microprocessor architecture. With my
proposed architecture, programmer can program in C/C++ language without
any knowledge about hardware architecture. It is different from writing
VHDL or Verilog code for FPGA which requires knowledge of hardware
achitecture, slides available, clock synchronization... Moreover, we
can use only one common hardware architecture (processor, memory, IO
devices) to run any application.

I call this architecture is "Network-on-Chip Dataflow Architecture". I
list here 7 important characteristics of it:

1. The Network-on-Chip Dataflow Architecture have many processing
elements (hundreds or thousands) so its performance is extremely high.
2. Each processing element in the Network-on-Chip Dataflow Architecture
needs only a small amount of bandwidth so that congestion in off-chip
interface can be avoided.
3. The Network-on-Chip Dataflow Architecture is very scalable so the
design task is very simple.
4. In the Network-on-Chip Dataflow Architecture, it is possible and
easy to control many (hundreds or thousands) processing elements
simultaneously.
5. In the Network-on-Chip Dataflow Architecture, it is possible and
easy to detect the dependency within many (hundreds or thousands)
instructions.
6. In the Network-on-Chip Dataflow Architecture, the power consumption
is low.
7. In the Network-on-Chip Dataflow Architecture, the clock frequency is
high.

You can find the detail of this architecture in this website:
www.nguyentl.netfirms.com

.

Relevant Pages

  • New Microprocessor architecture
    ... I have a new idea about microprocessor achitecture. ... it is slow because instructions are implemented sequencially. ... when CPU runs instructions within loops its operations is partially ... Each processing element in the Network-on-Chip Dataflow Architecture ...
    (comp.arch)
  • Re: New Microprocessor architecture
    ... between current microprocessors and FPGA. ... CPU is very flexible, it can run any ... it is slow because instructions are implemented sequencially. ... Each processing element in the Network-on-Chip Dataflow Architecture ...
    (comp.arch.arithmetic)