Re: Wire ORing in high speed logic!
- From: glen herrmannsfeldt <gah@xxxxxxxxxxxxxxxx>
- Date: Wed, 30 Aug 2006 23:53:42 -0700
Steve Richfie1d wrote:
Yes, I know, wire ORing is a microsecond method in a nanosecond world. However, there DOES appear to be a high speed way to do this, and a really good application for it!
Suppose that the bus that is to be wire OR'd is first yanked to one state, say False, and then the yanker goes high Z and the "1" data bits to be OR'd is then pulled True. This would perform the OR function in nanosecond(s) rather than in microseconds because there would be no resistors involved. Bus capacitance would keep open lines from drifting too far for the nanosecond(s) needed to do this, though pessimists could throw in a few useless pull-down resistors.
Since about the 0.6 micron days you can't ignore the resistance
of metal lines. At about 0.8 micron or more, once can consider a
wire as being connected to a lump capacitor to ground. It was
considered a big deal to change the tools to do the right timing
simulations for wires with resistance.
As the geometry scales by a factor of X, the capacitance (per unit length) scales by X, but the resistance per unit length scales as
X**-2.
Otherwise, your idea sounds similar to the way dynamic RAM read
is done. At the beginning, there is a precharge step where the
read line is charged to a specific voltage. The appropriate
transistor is activated to connect the desired bit to the read
line, and the new voltage is measured. by the sense amplifier.
That then determines the value of the stored bit.
Many FPGA's originally allowed for tri-state drivers, though not usually
wired-OR logic. As the devices scaled, at some point it became necessary to put buffers in the middle of lines. For a tri-state
line, it wouldn't be known which way to make the buffer, so they
now implement them as MUX logic instead.
-- glen
.
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