Re: Superstitious learning in Computer Architecture

On Thu, 24 Aug 2006 11:21:53 -0600, Steve Richfie1d wrote:
Perhaps I didn't make myself 100% clear. There is an easy order of
magnitude in speed available by simply switching over to the CDC Cyber
200 series architecture.

No there isn't. We are well and truly memory/pin bandwidth limited, these
days. At least for large data sets.

In present computationally limited applications, the loops do indeed
tend to be larger than 10 elements, and so the CDC architecture would
seem to be preferred.

A lot of computational code, these days, relies on bags of quite small
vectors, at least partly because of the object oriented way that they've
been coded.

Even without going to logarithmic ALUs or wafer scale integration, there
is STILL an easy order of magnitude left to be collected by abandoning
the scalar-only architecture of the Pentium.

That was abandoned years ago. All modern CPUs do vector arithmetic.

Note that the CDC Cyber 200 had NO CACHE!!! Why? It had little use for
it! The need for cache is architecture dependent - they just dug a
cache-dependent hole with the Pentium architecture. The array operations
in the Cyber 200 used a pipelining approach similar to the burst mode
used in present-day RAM chips, and the CPU had 256 registers.

I suspect that you would enjoy coding the CELL PE processors...

Cheers,

--
Andrew

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