Re: Decimal carry-save adder using reversed biquinary notation



John Savard wrote:

(big snip)

I've thought a little more about this, and I realize now why I
overlooked the possibility suggested.

Turning pairs of numbers into numbers with carries is what the first
stage of the Wallace tree would do anyways. So the only question is
whether my quibinary/biquinary trick would be faster than a few stages
of carry-save addition, one less than the total his suggestion required,
and I still feel it might be.

I first learned about carry save adders from the description of the
multiply (and divide) unit for the IBM 360/91. The 91 was always
a popular machine to describe in books on pipelined processors.
The 91 uses an iterative algorithm, sometimes described as Newton-
Raphson, which I would only suggest for floating point, but I believe
floating point is what we are discussing.

But then I realized that I was missing something even more important;
since a carry only has two values, that can be exploited *in the whole
Wallace tree*. A circuit that counts nine input signals, and outputs a
coded digit (in my circuit, in quibinary form) might involve delay as
well, though.

The limit depends on how wide (how many inputs) the available gates are.
For CMOS the width tends to be small, so it might take more levels than
one would like.

(snip)

-- glen

.



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