On 26-09-2005, khubaib <khubaib92@xxxxxxxxx> wrote: > I am searching for a fast CMOS VLSI adder desgin, that offers the least
> delay. At this time, I am not much concerned with the power and area of
> the 16-bit adder (untill the area does not affect the worst case
> delay).
> Can anybody point me to some resources and papers?. Any reading
> materials?. What would be the factors that would affect the worst case
> delay of a 16 bit adder?. It is a fixed point integer adder.
Re: Buffering the critical path. ... In my design i am using a 32 bit adder and some combinational logic ...delay between the combinational logic. ... big carry chain is causing the trouble in the router. ... The problem comes about from using many levels of logic (ie the signal goes through lots of LUTs) between the flip-flops plus the propagation delay associated with the carry chain. ... (comp.arch.fpga)
Re: Multiple simulations with different parameters ... Suppose I have a full adder with carry delay as a parameter. ...instantiate an existing full adder with different parameter values, ... you cannot modify the adder. ... (comp.lang.verilog)
fast VLSI adder desgin ... I am searching for a fast CMOS VLSI adder desgin,... I am not much concerned with the power and area of ...delay).... (comp.arch.arithmetic)
Re: Buffering the critical path. ... In my design i am using a 32 bit adder and some combinational logic ... The full path i want to constrain to double the clock ...delay between the combinational logic. ... Will this buffering ease the routing effort. ... (comp.arch.fpga)
Multiple simulations with different parameters ... I am a bit inexperienced with Verilog so please pardon me if my ... Suppose I have a full adder with carry delay as a parameter. ... (comp.lang.verilog)
