Re: About some parts on logical circuits

On Wed, 23 May 2007 01:41:44 +0200, "Dr Gang" <dr.gang@xxxxxxx> wrote:

Basically, you don't know what you're doing...

That's right.

Hey, don't worry. This is 5v, so you can't fry yourself. It's a great
way to learn.

I'll try to be clearer here :

From what I know about logical ICs, they understand 2 states : high (VCC)
and low (GND). My idea of a logical circuit is that the ICs output the right
voltage (that's the sure part) and the right intensity to actually activate
the other ICs (that's the less sure part that may involve resistors). My
guess is that logical ICs are designed to output the right voltage and
current to activate efficiently any other logical IC along its path but I'd
like to be sure.

That would be correct as long as every input is accounted for. Older
TTL circuits would predictably float high, but that's not always the
case for CMOS. So an unconnected input to a CMOS chip should be tied
to the appropriate logic level.

I didn't see the resistors that you were referring to. Was this by any
chance on some pushbutton switch logic? Often you will see a cap and
resistor in a debounce circuit.

The transistor part brings no interrogation (maybe it should...).

If you want to take a look at the schematic, here it is :
http://dr.gang.free.fr/test/Swtiching.pdf

The ICs are dual JK flip flops and a quad OR gates. The schematic shows JFET
transistors but I'll use more common NPN ones.

There's a difference in the way that a bipolar loads the JK's output
pin as compared to a FET, but you probably won't have any problems.

Thanks for your answers, even the sarcastic ones.

You're doing the best thing...just proceed with reckless abandon and
have fun. Really. With +5 volts you won't kill anybody.

I suggest that you change a couple things on your schematics: Don't
bother snaking the +5 or ground lines around. They clutter the
drawing. Use a small filled-in up-arrow for +. Use a larger hollow
triangle pointing down for ground (like Fender schematics). Draw those
right at the chips or wherever. Actually you don't have to draw any
power connects to the chips if you're posting something for us. People
know they're powered.

And change to individually drawn FF's and gates. Rather than drawing
the package outline, draw the bullet-shaped logic symbols for AND/OR
and individual boxes for the FFs. It makes your intent more clear.

Speaking of intent, what are you going for here?

.

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