Re: Isn't Command Rate a "memory setting?"

In article <1146671668.389336.70940@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>,
"milleron" <miller.90@xxxxxxxxx> wrote:

I'm having trouble with RAM again on my A8N-SLI Premium -- two sticks
of 512MB, 1GB total. I've already had Corsair replace my first set of
TwinX DIMMs, and all was well. However, after about four more months,
I started getting BSODs again and seeing errors in Prime95 AND in
Memtest86. If I set the command rate to 2T, then the computer's stable
at a CAS of 2.5. If I set the CAS to 3, then the computer's stable at
a command rate of 1T. CAS 2/1T and CAS 2.5/1T cause random BSODs and
errors in the memory-testing apps.

Ram Guy on the Corsair forum, however, is telling me that Command Rate
is not a memory setting. In my BIOS the setting is under "DRAM
Configuration," and it's labeled "1T/2T Memory Timing," but this guy is
telling me that it's NOT a memory setting. To his credit, he says that
if either stick, but not both, gives errors in Memtest86 at 2-2-2-5/1T,
then he will classify that stick as bad and replace it. That seems
correct and fair, but he says that if both, installed singly, give
errors at 2-2-2-5/1T, then the problem is in the motherboard or PSU,
and I don't see how he can jump to that conclusion. I don't see why
that couldn't be from both DIMMs being faulty.

I paid a premium for XMS 3200XLPT that's rated at 2-2-2-5, but I cannot
run it that way (or even at 2.5-3-3-5) with a command rate of 1T. To
me that's not up to spec, but Ram Guy says that as long as it will run
at their spec and 2T, the memory's OK. Doesn't this sound bogus?

Has anyone been UNable to run two 512MB sticks at 1T on this board?

Ron

I see a thread here, but I notice they didn't take you up on
offering a post mortem on the returned product :-)

http://www.houseofhelp.com/v2/showthread.php?t=44992&page=3&highlight=milleron

Command Rate is a memory controller issue. It has to do with the
inability of a memory controller driver, to drive an excessive
number of memory chips, and still meet the setup time.

As a general rule, a memory controller should be able to drive
one double sided DIMM (per channel) at 1T. The "four bank case",
of two double sided DIMMs, is when 2T would normally be suggested.
But in the overclocking community, 2T is sometimes used, to allow
a higher clock frequency, but that is kinda self defeating, unless
it allowed a huge extra overclock to happen.

I spent several hours today, working on the "2T thing". I've
tried searching in the past, for a diagram of the DDR interface
signals, showing 2T being used, but I've never been able to
find a diagram. The closest I ever got in the past, was some
analog simulations of 1T versus 2T, in a Micron application note.

Desktop computer chipset makers don't feel inclined to show
timing diagrams. So, I tried a different tack today. I looked
for an embedded controller capable of driving DDR, and with the
provision to support 2T timing. This is the result. (Freescale
is formerly known as Motorola.)

http://www.freescale.com/files/32bit/doc/app_note/AN2582.pdf

This embedded processor has a DDR controller built into it.
That makes it similar in a way, to the Athlon64.

Pg.36
"The 2T clock timing affects only the following signals:
MA[14:0], BA[1:0], RAS, CAS, WE. CS, CKE, and the data
bus are not affected by the double clock option."

"CAUTION: Again, neither the chip select, clock enable, nor
the data signals are affected by the 2T option. Because
MCS[0:3] and MCKE[0:1] <<chip select and clock enable>>
are referenced to the interface clock, they must still meet
a single clock cycle. Because both signal types are less
loaded than the other DDR groups, 1T timing is more achievable
for these signals. To ensure these signals meet 1T timing, the
designer should construct a separate budget and simulate these
signals accordingly so that proper termination and routing
constraints are applied to them."

This is my interpretation of the two timing cases. (Apologies
to Google readers. You can thank Google for completely fouling up
my diagrams! The diagrams will render properly using a fixed
font and your favorite USENET news reader. Google likes to
insert space characters, wherever they feel like. It means I
cannot expect to copy this diagram from a Google search in the
future and immediately repost it, without fixing whatever
they do to it.)

-------------------- Command Rate 1T Timing Diagram ------------
Command_Sampling_Point ^ (sampled on rising edge)

(Command_Issued) <-----------> (Issued in 1T period)
_____ _____ _____
Clock _____| |_____| |_____| |_____|
___________
MA/BA/RAS/CAS/WE -----------X___________X--------
___________ ________
ChipSelect_CS \___________/

-------------------- Command Rate 2T Timing Diagram ------------
Command_Sampling_Point ^ (rising)

(Command_Issued) <-----------------------> (2T period)
_____ _____ _____
Clock _____| |_____| |_____| |___
_______________________
MA/BA/RAS/CAS/WE -----------X_______________________X---
_______________________ ___
ChipSelect_CS \___________/

In the Command Rate 2T case, the chipset presents control
information for two cycles. AFAICT the chipselect signal
qualifies the command on the command/address bus, basically
telling the memory chip to sample the data. (I assume chipselect
is active low in the above diagram.) I show the command and the
chipselect signals as offset by half a cycle, because I believe
they are launched on falling edge, and are sampled at the memory
chips on the rising edge. I could have that wrong...

The performance difference between the two cases is, a DDR400
RAM, with a 200MHz clock, can complete 200 million commands
per second, if the 1T style interface is used. The command
rate drops to 100 million per second, if each one takes
two cycles instead. The DDR protocol doesn't keep the
address/command bus filled, and that is why the impact is a lot
smaller than the ratio of two numbers would suggest.

The next issue, is interpreting your hardware symptoms. You
are running the memory at higher than the JEDEC recommended
voltage. Could there be an electromigration issue with the
RAM ? If there was, those modules would be dying like flies,
and the RAM guy would "head for the hills".

And yet, what you seem to be saying, is the modules are
"wearing out" while they are in your computer.

Since you only have two sticks in there, it is hard to imagine
a timing conflict (timing overlap) between chips, is drawing
totem pole current. Do the modules get extremely hot ? Have
you placed a finger on them ? Heat might be one way to detect a
problem with the environment they are in.

Maybe the Vdimm circuit is overvolting ? Maybe it is delivering
more than the voltage stated in the BIOS ? That would be a
motherboard hardware problem. You'd need a multimeter to check
the voltage on the DIMM. The easiest way to do that, would be
to get a pinout for DDR, and find the power pin numbers,
then probe the contact of a particular power pin with a needle
fastened to the end of a multimeter probe. (I keep two needles
affixed to the ends of my multimeter probes, for stuff like this.)

If there was degradation, and no replacement module could fix it,
you would be assuming a processor wearout effect was present, and
your processor needed to be RMAed. If replacing the modules causes
you to regain use of the machine, then that tells you the poor
memory modules are the victim.

The integrated memory controller in your processor also has a
maximum voltage that can be applied to it. It is 2.9V. Overclockers
apply more than that to their processors, and one expert has
suggested, that to prevent damaging the processor, it is best
to raise Vcore at the same time as Vdimm, based on the suggestion
that it is the _difference_ in voltage between Vcore and Vdimm
that has killed some FX processors. That is for people who apply
excessively high voltages with DIMM boosters and the like. It
doesn't imply that you need to worry about this - it is for people
applying more than 2.9V to their memory. There is no way to prove
that, based on reading an AMD data***.

And the RAM guy was probably assuming that the odds of two DIMMs
failing at the same time, was too remote to consider. He lacks
imagination...

"but Ram Guy says that as long as it will run at their spec and 2T,
the memory's OK. Doesn't this sound bogus?" Yes, that is bull***.
The _memory_ is designed for Command Per Clock operation. The
2T command rate option is within the synchronous protocol between
memory controller and memory chip. With a single DIMM per channel,
the motherboard memory controller can select 1T operating mode,
and the module has to eat it. Claiming the module only has to do
2T is a crock. Or at least their docs should say "2-2-2-5 2T" if
they want to play such a game and avoid legal action. While it is
fine to _suggest_ 2T to reach DDR600, at a normal JEDEC rate like
DDR400 that should not be manditory. If only 2T command rate will
make the module work, that doesn't mean the module is meeting timing.
It could mean the 2T command rate, is compensating for a timing
parameter failure on the chips. (In the same way that 2T was needed on
Nforce2, to allow close to DDR400 operation. A "fast" module
didn't need 2T. There seems to be interaction between Command
Rate and the other four timing parameters, and using 2T on a
lightly loaded memory bus, appears to be a "crutch".)

Here are a few more URLs I visited today. I've placed them
here for myself, whenever I hit this thread in a future Google
search :-) The "breadcrumb method".

-----------------------------------------------------------------
"Command Per Clock, is a motherboard timing not a memory timing."
http://forums.pcper.com/showthread.php?t=383779

"Try switching ram from slot 1-2 to 3-4"
http://www.xbitlabs.com/forum/viewtopic.php?t=8071

"Processor revision and DIMM capacity 512MB vs 1GB makes a difference"
http://www.anandtech.com/memory/showdoc.aspx?i=2560&p=3

(Testing 1GB capacity sticks here. The plot of timing versus freq
is interesting, and the chip brand does make a difference in
behavior.)

http://www.xbitlabs.com/articles/memory/display/2gb-roundup.html

(The chart here, shows memory frequency is the most important factor
in performance. It looks like slacking the timing, cranking the
clock, gives the best benchmarks. And you would want to do this
at 1T if possible, as using 2T requires a huge increase in clock
rate to make up the performance loss. And the difference is a
3% improvement in SuperPI, not much diff in 3D performance.)

http://www.xbitlabs.com/articles/memory/display/patriot-ddr700_8.html

DRAM Command Rate defined but no diagram.
http://www.lostcircuits.com/memory/ddr2/4.shtml
-----------------------------------------------------------------

Paul
.