Re: P2B-S Ram Problem

In article <jLKhf.7560$e43.417731@xxxxxxxxxxxxxxxxxxxxx>, P2B
<p2b@xxxxxxxxxxxx> wrote:

> Mike wrote:
> > By the way this is a P2B-S Revision 1.02, I think it has bios version 1.14,
> > but I am not sure of that and will look if that is an issue, Thanks, Mike
> >
> > The Kingston site says the board calls for
> > KVR100X64C3/256
> > 256MB 100MHz Non-ECC CL3 DIMM
> > Standard 32M X 64 Non-ECC 100MHz 168-pin Unbuffered DIMM (SDRAM, 3.3V, CL3,
> > Gold
> >
> > Will CompUSA exchange these lifetime memory modules for the PC100 if
that is
> > my problem?
> >
> > "Mike" <recons@xxxxxxxxxx> wrote in message
> > news:CXIhf.1778$Un7.1063@xxxxxxxxxxx
> >
> >>Why is it that when I put two 256 mb SDRAM sticks in I don't get 512 I
> >>continue to get 256? This is Kingston KVR133X64C2/256.
> >>256MB 133MHz Non-ECC CL2 DIMM
> >>Standard 32M X 64 Non-ECC 133MHz 168-pin Unbuffered DIMM (SDRAM, 3.3V,
> >>CL2, Gold
> >>
> >>What am I missing? Thanks guys this board has always been very helpful,
> >>Mike
>
> KVR133X64C2/256 has 8 chips internally organised as 8M x 8-bit x 4 banks:
>
> http://www.valueram.com/datasheets/KVR133X64C2_256.pdf
>
> KVR100X64C3/256 has 16 chips internally organised as 16M x 8-bit x 2 banks:
>
> http://www.valueram.com/datasheets/KVR100X64C3_256.pdf
>
> The 440BX chipset on the P2B-S only supports 2 banks (aka double-sided),
> so it only sees half of the 4-bank KVR133X64C2/256 modules you
> purchased. The 2-bank KVR100X64C3/256 modules will work at full capacity.
>
> P2B

There are "ranks" and there are "banks". A double sided DIMM is
two "ranks". The structure inside each chip is the "banks".
(At least I've seen "ranks" used to break the naming convention
problem of both levels using the term "banks".)

>From the 440BX data***, it says:

DRAM type: Extended Data Out (EDO) (mobile only) or Synchronous
(SDRAM) DRAM controller optimized for dual/quad-bank SDRAM
organization on a row by row basis

Further in the data***, there is a reference to quad bank
(inside-the-chip banks) addressing as well. BA[1:0] would
address four internal chip banks:

MAA/B[12:11] function as Bank Addresses
(BA[1:0], or Bank Selects).

I thought the deal with 32Mx8 versus 16Mx8, was one of addressing
bits. I think the chip has 12 true address bits, and the two bits
functioning as BA[1:0]. A 32Mx8 chip can have an orientation of
13 x 10 (plus the two bank bits), which is one too many to be
addressed by a 12 address Northbridge. I could be mistaken.

Rows, columns, banks, ranks. I think the problem needs more
dimensions :-)

Paul
.